Add grabber module

(cherry picked from commit b768d5648c)
Signed-off-by: Egor Savkin <es@m-labs.hk>

src/gateware/kasli_soc.py

@@ -114,7 +114,7 @@ class SMAClkinForward(Module):
 class GenericStandalone(SoCCore):
     def __init__(self, description, acpki=False):
         self.acpki = acpki
-        rtio_clk_freq = description["rtio_frequency"]
+        sys_clk_freq = 125e6
 
         platform = kasli_soc.Platform()
         platform.toolchain.bitstream_commands.extend([
@@ -143,7 +143,7 @@ class GenericStandalone(SoCCore):
             self.ps7.cd_sys.clk,
             self.rtio_crg.cd_rtio.clk)
         fix_serdes_timing_path(platform)
-        self.config["CLOCK_FREQUENCY"] = int(rtio_clk_freq)
+        self.config["CLOCK_FREQUENCY"] = int(sys_clk_freq)
 
         self.rtio_channels = []
         has_grabber = any(peripheral["type"] == "grabber" for peripheral in description["peripherals"])
@@ -228,7 +228,7 @@ class GenericMaster(SoCCore):
             pads=data_pads,
             sys_clk_freq=sys_clk_freq)
         self.csr_devices.append("drtio_transceiver")
-        self.config["CLOCK_FREQUENCY"] = int(rtio_clk_freq)
+        self.config["CLOCK_FREQUENCY"] = int(sys_clk_freq)
 
         self.crg = self.ps7 # HACK for eem_7series to find the clock
         self.submodules.rtio_crg = RTIOClockMultiplier(rtio_clk_freq)
@@ -461,7 +461,7 @@ class GenericSatellite(SoCCore):
 
         rtio_clk_period = 1e9/rtio_clk_freq
         self.config["RTIO_FREQUENCY"] = str(rtio_clk_freq/1e6)
-        self.config["CLOCK_FREQUENCY"] = int(rtio_clk_freq)
+        self.config["CLOCK_FREQUENCY"] = int(sys_clk_freq)
 
         self.submodules.siphaser = SiPhaser7Series(
             si5324_clkin=platform.request("cdr_clk"),