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d1705113aa
Author | SHA1 | Date |
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mwojcik | d1705113aa | |
mwojcik | 97dfa07bdb |
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@ -187,6 +187,9 @@ class GenericMaster(SoCCore):
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mem_map.update(SoCCore.mem_map)
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def __init__(self, description, acpki=False):
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sys_clk_freq = 800e6 # this is not set within SoCCore anymore, but rather - by SZL?
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# not sure if it should be ArmPLL/CPU/IoPLL freq - they differ slightly
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# necessary for GTX transceiver
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rtio_clk_freq = 125e6 # should this be pulled from description? rtio freq isnt set
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self.acpki = acpki
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@ -207,11 +210,20 @@ class GenericMaster(SoCCore):
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# kasli_soc has no SATA, but it has 4x SFP
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# not sure yet why sfp0 is omitted in MasterMode
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drtio_data_pads = [platform.request("sfp", i) for i in range(4)]
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drtio_tx_pads = []
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drtio_rx_pads = []
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for sfp in drtio_data_pads:
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drtio_tx_pads += [sfp.txp, sfp.txn]
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drtio_rx_pads += [sfp.rxp, sfp.rxn]
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# this does not work for now ^ GTX expects p/n subsignals in tx/rx signals,
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# rather than txp/txn ... subsignals
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# probably need to modify kasli_soc platform in migen
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self.submodules.drtio_transceiver = gtx_7series.GTX(
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clock_pads=platform.request("clk125_gtp"), # referred to as clk gtp in schematics, but for gtx?
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data_pads=drtio_data_pads,
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sys_clk_freq=self.clk_freq)
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tx_pads=drtio_tx_pads,
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rx_pads=drtio_rx_pads,
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sys_clk_freq=sys_clk_freq)
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self.csr_devices.append("drtio_transceiver")
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self.crg = self.ps7 # HACK for eem_7series to find the clock
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@ -319,7 +331,11 @@ class GenericSatellite(SoCCore):
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mem_map.update(SoCCore.mem_map)
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def __init__(self, description, acpki=False):
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rtio_clk_freq = 125e6 # same thing as with master
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sys_clk_freq = 800e6 # this is not set within SoCCore anymore, but rather - by SZL?
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# not sure if it should be ArmPLL/CPU/IoPLL freq - they differ slightly
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# necessary for GTX transceiver
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rtio_clk_freq = 125e6 # same thing as with master - pulled from desc?
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# will probably be replaced with rtio_config key as per #1735
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self.acpki = acpki
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self.rustc_cfg = dict()
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@ -337,11 +353,17 @@ class GenericSatellite(SoCCore):
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platform.add_platform_command("set_input_jitter clk_fpga_0 0.24")
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drtio_data_pads = [platform.request("sfp", i) for i in range(4)]
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drtio_tx_pads = []
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drtio_rx_pads = []
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for sfp in drtio_data_pads:
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drtio_tx_pads += [sfp.txp, sfp.txn]
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drtio_rx_pads += [sfp.rxp, sfp.rxn]
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self.submodules.drtio_transceiver = gtx_7series.GTX(
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clock_pads=platform.request("clk125_gtp"), # referred to as clk gtp in schematics, but for gtx?
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data_pads=drtio_data_pads,
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sys_clk_freq=self.clk_freq)
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tx_pads=drtio_tx_pads,
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rx_pads=drtio_rx_pads,
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sys_clk_freq=sys_clk_freq)
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self.csr_devices.append("drtio_transceiver")
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self.crg = self.ps7 # HACK for eem_7series to find the clock
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@ -269,6 +269,9 @@ class Master(ZC706):
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def __init__(self, **kwargs):
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ZC706.__init__(self, **kwargs)
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sys_clk_freq = 800e6 # same as in Kasli-SoC - CPU freq set by SZL
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# again not sure if correct value
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platform = self.platform
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self.comb += platform.request("sfp_tx_disable_n").eq(1)
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@ -284,7 +287,7 @@ class Master(ZC706):
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clock_pads=platform.request("si5324_clkout"),
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tx_pads=tx_pads,
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rx_pads=rx_pads,
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sys_clk_freq=self.clk_freq)
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sys_clk_freq=sys_clk_freq)
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self.csr_devices.append("drtio_transceiver")
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self.submodules.rtio_tsc = rtio.TSC("async", glbl_fine_ts_width=3)
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@ -370,6 +373,8 @@ class Satellite(ZC706):
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def __init__(self, **kwargs):
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ZC706.__init__(self, **kwargs)
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sys_clk_freq = 800e6 # same as in Kasli-SoC - CPU freq set by SZL
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# again not sure if correct value
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platform = self.platform
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@ -386,7 +391,7 @@ class Satellite(ZC706):
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clock_pads=platform.request("si5324_clkout"),
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tx_pads=tx_pads,
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rx_pads=rx_pads,
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sys_clk_freq=self.clk_freq)
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sys_clk_freq=sys_clk_freq)
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self.csr_devices.append("drtio_transceiver")
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self.submodules.rtio_tsc = rtio.TSC("sync", glbl_fine_ts_width=3)
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@ -16,7 +16,7 @@ extern crate libregister;
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extern crate alloc;
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use libboard_zynq::{i2c::I2c, timer::GlobalTimer, time::Milliseconds, print, println, mpcore, gic};
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use libboard_zynq::{i2c::I2c, timer::GlobalTimer, time::Milliseconds, print, println, mpcore, gic, stdio};
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use libsupport_zynq::ram;
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#[cfg(has_si5324)]
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use libboard_artiq::si5324;
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@ -580,6 +580,7 @@ interrupt_handler!(IRQ, irq, __irq_stack0_start, __irq_stack1_start, {
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notify_spin_lock();
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main_core1();
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}
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stdio::drop_uart();
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}
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loop {}
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});
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