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e3d01fb7ac
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131c7103df
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@ -1,16 +0,0 @@
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from misoc.integration import cpu_interface
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def write_csr_file(soc, filename):
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with open(filename, "w") as f:
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f.write(cpu_interface.get_csr_rust(
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soc.get_csr_regions(), soc.get_csr_groups(), soc.get_constants()))
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def write_mem_file(soc, filename):
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with open(filename, "w") as f:
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f.write(cpu_interface.get_mem_rust(
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soc.get_memory_regions(), soc.get_memory_groups(), None))
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def write_rustc_cfg_file(soc, filename):
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with open(filename, "w") as f:
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f.write(cpu_interface.get_rust_cfg(
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soc.get_csr_regions(), soc.get_constants()))
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@ -11,6 +11,7 @@ from migen_axi.integration.soc_core import SoCCore
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from migen_axi.platforms import kasli_soc
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from migen_axi.platforms import kasli_soc
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from misoc.interconnect.csr import *
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from misoc.interconnect.csr import *
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from misoc.cores import virtual_leds
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from misoc.cores import virtual_leds
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from misoc.integration import cpu_interface
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from artiq.coredevice import jsondesc
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from artiq.coredevice import jsondesc
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from artiq.gateware import rtio, eem_7series
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from artiq.gateware import rtio, eem_7series
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@ -26,7 +27,6 @@ import dma
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import analyzer
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import analyzer
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import acpki
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import acpki
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import drtio_aux_controller
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import drtio_aux_controller
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from config import write_csr_file, write_mem_file, write_rustc_cfg_file
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class RTIOCRG(Module, AutoCSR):
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class RTIOCRG(Module, AutoCSR):
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def __init__(self, platform):
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def __init__(self, platform):
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@ -496,6 +496,28 @@ class GenericSatellite(SoCCore):
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self.comb += [self.virtual_leds.get(i).eq(channel.rx_ready)
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self.comb += [self.virtual_leds.get(i).eq(channel.rx_ready)
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for i, channel in enumerate(self.drtio_transceiver.channels)]
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for i, channel in enumerate(self.drtio_transceiver.channels)]
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def write_mem_file(soc, filename):
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with open(filename, "w") as f:
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f.write(cpu_interface.get_mem_rust(
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soc.get_memory_regions(), soc.get_memory_groups(), None))
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def write_csr_file(soc, filename):
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with open(filename, "w") as f:
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f.write(cpu_interface.get_csr_rust(
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soc.get_csr_regions(), soc.get_csr_groups(), soc.get_constants()))
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def write_rustc_cfg_file(soc, filename):
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with open(filename, "w") as f:
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for name, origin, busword, obj in soc.get_csr_regions():
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f.write("has_{}\n".format(name.lower()))
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for name, value in soc.get_constants():
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if name.upper().startswith("CONFIG_"):
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if value is None:
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f.write("{}\n".format(name.lower()[7:]))
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else:
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f.write("{}=\"{}\"\n".format(name.lower()[7:], str(value)))
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def main():
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def main():
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@ -10,6 +10,7 @@ from migen.genlib.cdc import MultiReg
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from migen_axi.integration.soc_core import SoCCore
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from migen_axi.integration.soc_core import SoCCore
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from migen_axi.platforms import zc706
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from migen_axi.platforms import zc706
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from misoc.interconnect.csr import *
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from misoc.interconnect.csr import *
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from misoc.integration import cpu_interface
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from misoc.cores import gpio
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from misoc.cores import gpio
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from artiq.gateware import rtio, nist_clock, nist_qc2
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from artiq.gateware import rtio, nist_clock, nist_qc2
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@ -24,7 +25,6 @@ import dma
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import analyzer
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import analyzer
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import acpki
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import acpki
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import drtio_aux_controller
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import drtio_aux_controller
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from config import write_csr_file, write_mem_file, write_rustc_cfg_file
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class RTIOCRG(Module, AutoCSR):
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class RTIOCRG(Module, AutoCSR):
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@ -653,7 +653,27 @@ VARIANTS = {cls.__name__.lower(): cls for cls in [NIST_CLOCK, NIST_CLOCK_Master,
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NIST_QC2, NIST_QC2_Master, NIST_QC2_Satellite]}
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NIST_QC2, NIST_QC2_Master, NIST_QC2_Satellite]}
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def write_csr_file(soc, filename):
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with open(filename, "w") as f:
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f.write(cpu_interface.get_csr_rust(
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soc.get_csr_regions(), soc.get_csr_groups(), soc.get_constants()))
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def write_mem_file(soc, filename):
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with open(filename, "w") as f:
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f.write(cpu_interface.get_mem_rust(
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soc.get_memory_regions(), soc.get_memory_groups(), None))
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def write_rustc_cfg_file(soc, filename):
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with open(filename, "w") as f:
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for name, origin, busword, obj in soc.get_csr_regions():
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f.write("has_{}\n".format(name.lower()))
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for name, value in soc.get_constants():
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if name.upper().startswith("CONFIG_"):
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if value is None:
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f.write("{}\n".format(name.lower()[7:]))
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else:
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f.write("{}=\"{}\"\n".format(name.lower()[7:], str(value)))
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def main():
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def main():
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