src/gateware/config.py

@@ -1,16 +0,0 @@
-from misoc.integration import cpu_interface
-
-def write_csr_file(soc, filename):
-    with open(filename, "w") as f:
-        f.write(cpu_interface.get_csr_rust(
-            soc.get_csr_regions(), soc.get_csr_groups(), soc.get_constants()))
-
-def write_mem_file(soc, filename):
-    with open(filename, "w") as f:
-        f.write(cpu_interface.get_mem_rust(
-            soc.get_memory_regions(), soc.get_memory_groups(), None))
-
-def write_rustc_cfg_file(soc, filename):
-    with open(filename, "w") as f:
-        f.write(cpu_interface.get_rust_cfg(
-            soc.get_csr_regions(), soc.get_constants()))

src/gateware/kasli_soc.py

@@ -11,6 +11,7 @@ from migen_axi.integration.soc_core import SoCCore
 from migen_axi.platforms import kasli_soc
 from misoc.interconnect.csr import *
 from misoc.cores import virtual_leds
+from misoc.integration import cpu_interface
 
 from artiq.coredevice import jsondesc
 from artiq.gateware import rtio, eem_7series
@@ -26,7 +27,6 @@ import dma
 import analyzer
 import acpki
 import drtio_aux_controller
-from config import write_csr_file, write_mem_file, write_rustc_cfg_file
 
 class RTIOCRG(Module, AutoCSR):
     def __init__(self, platform):
@@ -496,6 +496,28 @@ class GenericSatellite(SoCCore):
         self.comb += [self.virtual_leds.get(i).eq(channel.rx_ready)
                 for i, channel in enumerate(self.drtio_transceiver.channels)]
 
+def write_mem_file(soc, filename):
+    with open(filename, "w") as f:
+        f.write(cpu_interface.get_mem_rust(
+            soc.get_memory_regions(), soc.get_memory_groups(), None))
+
+
+def write_csr_file(soc, filename):
+    with open(filename, "w") as f:
+        f.write(cpu_interface.get_csr_rust(
+            soc.get_csr_regions(), soc.get_csr_groups(), soc.get_constants()))
+
+
+def write_rustc_cfg_file(soc, filename):
+    with open(filename, "w") as f:
+        for name, origin, busword, obj in soc.get_csr_regions():
+            f.write("has_{}\n".format(name.lower()))
+        for name, value in soc.get_constants():
+            if name.upper().startswith("CONFIG_"):
+                if value is None:
+                    f.write("{}\n".format(name.lower()[7:]))
+                else:
+                    f.write("{}=\"{}\"\n".format(name.lower()[7:], str(value)))
 
 
 def main():

src/gateware/zc706.py

@@ -10,6 +10,7 @@ from migen.genlib.cdc import MultiReg
 from migen_axi.integration.soc_core import SoCCore
 from migen_axi.platforms import zc706
 from misoc.interconnect.csr import *
+from misoc.integration import cpu_interface
 from misoc.cores import gpio
 
 from artiq.gateware import rtio, nist_clock, nist_qc2
@@ -24,7 +25,6 @@ import dma
 import analyzer
 import acpki
 import drtio_aux_controller
-from config import write_csr_file, write_mem_file, write_rustc_cfg_file
 
 
 class RTIOCRG(Module, AutoCSR):
@@ -653,7 +653,27 @@ VARIANTS = {cls.__name__.lower(): cls for cls in [NIST_CLOCK, NIST_CLOCK_Master,
                                                   NIST_QC2, NIST_QC2_Master, NIST_QC2_Satellite]}
 
 
+def write_csr_file(soc, filename):
+    with open(filename, "w") as f:
+        f.write(cpu_interface.get_csr_rust(
+            soc.get_csr_regions(), soc.get_csr_groups(), soc.get_constants()))
 
+def write_mem_file(soc, filename):
+    with open(filename, "w") as f:
+        f.write(cpu_interface.get_mem_rust(
+            soc.get_memory_regions(), soc.get_memory_groups(), None))
+
+
+def write_rustc_cfg_file(soc, filename):
+    with open(filename, "w") as f:
+        for name, origin, busword, obj in soc.get_csr_regions():
+            f.write("has_{}\n".format(name.lower()))
+        for name, value in soc.get_constants():
+            if name.upper().startswith("CONFIG_"):
+                if value is None:
+                    f.write("{}\n".format(name.lower()[7:]))
+                else:
+                    f.write("{}=\"{}\"\n".format(name.lower()[7:], str(value)))
 
 
 def main():