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Author SHA1 Message Date
mwojcik 9bd07b0759 rtio_clocking: inform the user if PLL is bypassed 2023-10-06 16:25:33 +08:00
mwojcik 4dae3d77ee kasli_soc: support 100MHz clock 2023-10-06 16:25:33 +08:00
1 changed files with 3 additions and 3 deletions
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src/gateware/kasli_soc.py
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@ -66,15 +66,15 @@ class GTPBootstrapClock(Module):
self.clock_domains.cd_bootstrap = ClockDomain(reset_less=True)
self.cd_bootstrap.clk.attr.add("keep")
bootstrap = platform.request("clk125_gtp")
bootstrap_125 = platform.request("clk125_gtp")
bootstrap_se = Signal()
clk_out = Signal()
platform.add_period_constraint(bootstrap.p, 8.0)
platform.add_period_constraint(bootstrap_125.p, 8.0)
self.specials += [
Instance("IBUFDS_GTE2",
i_CEB=0,
i_I=bootstrap.p, i_IB=bootstrap.n,
i_I=bootstrap_125.p, i_IB=bootstrap_125.n,
o_O=bootstrap_se,
p_CLKCM_CFG="TRUE",
p_CLKRCV_TRST="TRUE",