rtio_clocking: inform the user if PLL is bypassed

src/gateware/kasli_soc.py

@@ -68,7 +68,6 @@ class GTPBootstrapClock(Module):
 
         bootstrap_125 = platform.request("clk125_gtp")
         bootstrap_se = Signal()
-
         clk_out = Signal()
         platform.add_period_constraint(bootstrap_125.p, 8.0)
         self.specials += [

src/runtime/src/rtio_clocking.rs

@@ -267,7 +267,7 @@ pub fn init(timer: &mut GlobalTimer, cfg: &Config) {
             RtioClock::Ext0_Bypass => {
                 info!("bypassing the PLL for RTIO clock");
                 si5324::bypass(i2c, SI5324_EXT_INPUT, timer).expect("cannot bypass Si5324")
-            },
+            }
             _ => setup_si5324(i2c, timer, clk),
         }
     }