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005f96a924
Author | SHA1 | Date |
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005f96a924 | |
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682e92b17e | |
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fbf973efd0 | |
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a163d29ec0 | |
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9d27741de8 |
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@ -594,7 +594,7 @@ class GenericSatellite(SoCCore):
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self.csr_devices.append("wrpll")
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self.csr_devices.append("wrpll")
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self.comb += self.ps7.core.core0.nfiq.eq(self.wrpll.ev.irq)
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self.comb += self.ps7.core.core0.nfiq.eq(self.wrpll.ev.irq)
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self.config["HAS_SI549"] = None
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self.config["HAS_SI549"] = None
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self.config["WRPLL_REF_CLK"] = "GTX_CDR"
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self.config["WRPLL_REF_CLK"] = "GT_CDR"
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else:
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else:
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self.submodules.siphaser = SiPhaser7Series(
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self.submodules.siphaser = SiPhaser7Series(
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si5324_clkin=platform.request("cdr_clk"),
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si5324_clkin=platform.request("cdr_clk"),
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@ -357,7 +357,7 @@ pub mod wrpll {
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mod tag_collector {
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mod tag_collector {
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use super::*;
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use super::*;
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#[cfg(wrpll_ref_clk = "GTX_CDR")]
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#[cfg(wrpll_ref_clk = "GT_CDR")]
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static TAG_OFFSET: Mutex<u32> = Mutex::new(19050);
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static TAG_OFFSET: Mutex<u32> = Mutex::new(19050);
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#[cfg(wrpll_ref_clk = "SMA_CLKIN")]
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#[cfg(wrpll_ref_clk = "SMA_CLKIN")]
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static TAG_OFFSET: Mutex<u32> = Mutex::new(0);
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static TAG_OFFSET: Mutex<u32> = Mutex::new(0);
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@ -457,7 +457,7 @@ pub mod wrpll {
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csr::wrpll::frequency_counter_update_en_write(1);
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csr::wrpll::frequency_counter_update_en_write(1);
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timer.delay_us(150_000); // 8ns << TIMER_WIDTH
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timer.delay_us(150_000); // 8ns << TIMER_WIDTH
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csr::wrpll::frequency_counter_update_en_write(0);
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csr::wrpll::frequency_counter_update_en_write(0);
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#[cfg(wrpll_ref_clk = "GTX_CDR")]
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#[cfg(wrpll_ref_clk = "GT_CDR")]
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let ref_count = csr::wrpll::frequency_counter_counter_rtio_rx0_read();
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let ref_count = csr::wrpll::frequency_counter_counter_rtio_rx0_read();
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#[cfg(wrpll_ref_clk = "SMA_CLKIN")]
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#[cfg(wrpll_ref_clk = "SMA_CLKIN")]
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let ref_count = csr::wrpll::frequency_counter_counter_ref_read();
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let ref_count = csr::wrpll::frequency_counter_counter_ref_read();
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@ -534,7 +534,7 @@ pub mod wrpll {
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Ok(())
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Ok(())
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}
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}
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#[cfg(wrpll_ref_clk = "GTX_CDR")]
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#[cfg(wrpll_ref_clk = "GT_CDR")]
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fn test_skew(timer: &mut GlobalTimer) -> Result<(), &'static str> {
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fn test_skew(timer: &mut GlobalTimer) -> Result<(), &'static str> {
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// wait for PLL to stabilize
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// wait for PLL to stabilize
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timer.delay_us(20_000);
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timer.delay_us(20_000);
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@ -547,7 +547,7 @@ pub mod wrpll {
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Ok(())
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Ok(())
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}
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}
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#[cfg(wrpll_ref_clk = "GTX_CDR")]
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#[cfg(wrpll_ref_clk = "GT_CDR")]
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fn has_timing_error(timer: &mut GlobalTimer) -> bool {
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fn has_timing_error(timer: &mut GlobalTimer) -> bool {
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unsafe {
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unsafe {
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csr::wrpll_skewtester::error_write(1);
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csr::wrpll_skewtester::error_write(1);
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@ -664,7 +664,7 @@ pub mod wrpll {
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#[cfg(feature = "calibrate_wrpll_skew")]
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#[cfg(feature = "calibrate_wrpll_skew")]
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calibrate_skew(timer).expect("failed to set the correct skew");
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calibrate_skew(timer).expect("failed to set the correct skew");
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#[cfg(wrpll_ref_clk = "GTX_CDR")]
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#[cfg(wrpll_ref_clk = "GT_CDR")]
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test_skew(timer).expect("skew test failed");
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test_skew(timer).expect("skew test failed");
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}
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}
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}
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}
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@ -688,12 +688,10 @@ pub mod wrpll_refclk {
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pub filt_reg2: u16, //0x4F
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pub filt_reg2: u16, //0x4F
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}
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}
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fn one_clock_cycle(timer: &mut GlobalTimer) {
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fn one_clock_cycle() {
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unsafe {
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unsafe {
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csr::wrpll_refclk::mmcm_dclk_write(1);
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csr::wrpll_refclk::mmcm_dclk_write(1);
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timer.delay_us(1);
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csr::wrpll_refclk::mmcm_dclk_write(0);
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csr::wrpll_refclk::mmcm_dclk_write(0);
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timer.delay_us(1);
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}
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}
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}
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}
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@ -732,33 +730,33 @@ pub mod wrpll_refclk {
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}
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}
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#[allow(dead_code)]
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#[allow(dead_code)]
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fn read(timer: &mut GlobalTimer, address: u8) -> u16 {
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fn read(address: u8) -> u16 {
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set_addr(address);
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set_addr(address);
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set_enable(true);
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set_enable(true);
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// Set DADDR on the MMCM and assert DEN for one clock cycle
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// Set DADDR on the MMCM and assert DEN for one clock cycle
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one_clock_cycle(timer);
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one_clock_cycle();
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set_enable(false);
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set_enable(false);
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while !drp_ready() {
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while !drp_ready() {
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// keep the clock signal until data is ready
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// keep the clock signal until data is ready
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one_clock_cycle(timer);
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one_clock_cycle();
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}
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}
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get_data()
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get_data()
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}
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}
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fn write(timer: &mut GlobalTimer, address: u8, value: u16) {
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fn write(address: u8, value: u16) {
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set_addr(address);
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set_addr(address);
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set_data(value);
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set_data(value);
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set_write_enable(true);
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set_write_enable(true);
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set_enable(true);
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set_enable(true);
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// Set DADDR, DI on the MMCM and assert DWE, DEN for one clock cycle
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// Set DADDR, DI on the MMCM and assert DWE, DEN for one clock cycle
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one_clock_cycle(timer);
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one_clock_cycle();
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set_write_enable(false);
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set_write_enable(false);
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set_enable(false);
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set_enable(false);
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while !drp_ready() {
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while !drp_ready() {
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// keep the clock signal until write is finished
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// keep the clock signal until write is finished
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one_clock_cycle(timer);
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one_clock_cycle();
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}
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}
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}
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}
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@ -783,17 +781,17 @@ pub mod wrpll_refclk {
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// Based on "DRP State Machine" from XAPP888
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// Based on "DRP State Machine" from XAPP888
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// hold reset HIGH during mmcm config
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// hold reset HIGH during mmcm config
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reset(true);
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reset(true);
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write(timer, 0x08, settings.clkout0_reg1);
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write(0x08, settings.clkout0_reg1);
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write(timer, 0x09, settings.clkout0_reg2);
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write(0x09, settings.clkout0_reg2);
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write(timer, 0x14, settings.clkfbout_reg1);
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write(0x14, settings.clkfbout_reg1);
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write(timer, 0x15, settings.clkfbout_reg2);
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write(0x15, settings.clkfbout_reg2);
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write(timer, 0x16, settings.div_reg);
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write(0x16, settings.div_reg);
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write(timer, 0x18, settings.lock_reg1);
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write(0x18, settings.lock_reg1);
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write(timer, 0x19, settings.lock_reg2);
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write(0x19, settings.lock_reg2);
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write(timer, 0x1A, settings.lock_reg3);
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write(0x1A, settings.lock_reg3);
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write(timer, 0x28, settings.power_reg);
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write(0x28, settings.power_reg);
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write(timer, 0x4E, settings.filt_reg1);
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write(0x4E, settings.filt_reg1);
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write(timer, 0x4F, settings.filt_reg2);
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write(0x4F, settings.filt_reg2);
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reset(false);
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reset(false);
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// wait for the mmcm to lock
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// wait for the mmcm to lock
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