Compare commits
6 Commits
38af2de0c0
...
b9fd750091
| Author | SHA1 | Date |
|---|---|---|
 mwojcik
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b9fd750091 | |
 linuswck
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e1b2c45813 | |
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linuswck
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e6372b9766 | |
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linuswck
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07044752b6 | |
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linuswck
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79fc5a7789 | |
 Sebastien Bourdeauducq
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d3f4602361 |
28
flake.lock
28
flake.lock
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@ -11,11 +11,11 @@
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"src-pythonparser": "src-pythonparser"
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},
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"locked": {
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"lastModified": 1697537883,
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"narHash": "sha256-GfadmYHFkczltX+rPf08YpAHjYa/31ZmmVD578BcFow=",
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"lastModified": 1699353408,
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"narHash": "sha256-mJZ9PoRsOvN5gtrEl9ogj/+GRCK8O3tZbcyfxKvGG20=",
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"ref": "refs/heads/master",
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"rev": "b168f0bb4be1697ff100475c20ee304dcc31fcc2",
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"revCount": 8573,
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"rev": "ec2b86b08d497a41e75c228385b754c6f3a4a8bf",
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"revCount": 8585,
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"type": "git",
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"url": "https://github.com/m-labs/artiq.git"
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},
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@ -118,11 +118,11 @@
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},
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"nixpkgs": {
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"locked": {
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"lastModified": 1697226376,
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"narHash": "sha256-cumLLb1QOUtWieUnLGqo+ylNt3+fU8Lcv5Zl+tYbRUE=",
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"lastModified": 1699169573,
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"narHash": "sha256-cvUb1xZkvOp3W2SzylStrTirhVd9zCeo5utJl9nSIhw=",
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"owner": "NixOS",
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"repo": "nixpkgs",
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"rev": "898cb2064b6e98b8c5499f37e81adbdf2925f7c5",
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"rev": "aeefe2054617cae501809b82b44a8e8f7be7cc4b",
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"type": "github"
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},
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"original": {
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@ -163,11 +163,11 @@
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"src-migen": {
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"flake": false,
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"locked": {
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"lastModified": 1697013661,
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"narHash": "sha256-qNCqgWyE4vTDmyjE2XMJqW1djuBxT25A36AzQfZqluU=",
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"lastModified": 1699335478,
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"narHash": "sha256-BsubN4Mfdj02QPK6ZCrl+YOaSg7DaLQdSCVP49ztWik=",
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"owner": "m-labs",
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"repo": "migen",
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"rev": "aadc19df93b7aa9ca761aaebbb98a11e0cf2d7c7",
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"rev": "fd0bf5855a1367eab14b0d6f7f8266178e25d78e",
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"type": "github"
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},
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"original": {
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@ -179,11 +179,11 @@
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"src-misoc": {
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"flake": false,
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"locked": {
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"lastModified": 1693709836,
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"narHash": "sha256-YiCk05RYLzZu1CYkQ2r7XtjwVEqkUGTQn388uOls9tI=",
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"lastModified": 1699352904,
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"narHash": "sha256-SglyTmXOPv8jJOjwAjJrj/WhAkItQfUbvKfUqrynwRg=",
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"ref": "refs/heads/master",
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"rev": "58dc4ee60d165ce9145cf3d904241fc154b6407f",
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"revCount": 2448,
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"rev": "a53859f2167c31ab5225b6c09f30cf05527b94f4",
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"revCount": 2452,
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"submodules": true,
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"type": "git",
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"url": "https://github.com/m-labs/misoc.git"
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@ -237,12 +237,16 @@ class GenericMaster(SoCCore):
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gtx0 = self.gt_drtio.gtxs[0]
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self.specials += Instance("BUFG", i_I=gtx0.txoutclk, o_O=txout_buf)
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ext_async_rst = Signal()
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self.submodules.bootstrap = GTPBootstrapClock(self.platform, clk_freq)
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self.submodules.sys_crg = zynq_clocking.SYSCRG(
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self.platform,
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self.ps7,
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txout_buf,
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clk_sw=gtx0.tx_init.done)
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clk_sw=self.gt_drtio.stable_clkin.storage,
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clk_sw_status=gtx0.tx_init.done,
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ext_async_rst=ext_async_rst)
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self.csr_devices.append("sys_crg")
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self.crg = self.ps7 # HACK for eem_7series to find the clock
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self.crg.cd_sys = self.sys_crg.cd_sys
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@ -250,6 +254,9 @@ class GenericMaster(SoCCore):
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self.bootstrap.cd_bootstrap.clk, self.sys_crg.cd_sys.clk)
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fix_serdes_timing_path(platform)
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self.comb += ext_async_rst.eq(self.sys_crg.clk_sw_fsm.o_clk_sw & ~gtx0.tx_init.done)
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self.specials += MultiReg(self.sys_crg.clk_sw_fsm.o_clk_sw & self.sys_crg.mmcm_locked, self.gt_drtio.clk_path_ready, odomain="bootstrap")
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self.config["HAS_SI5324"] = None
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self.config["SI5324_SOFT_RESET"] = None
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@ -419,12 +426,16 @@ class GenericSatellite(SoCCore):
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gtx0 = self.gt_drtio.gtxs[0]
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self.specials += Instance("BUFG", i_I=gtx0.txoutclk, o_O=txout_buf)
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ext_async_rst = Signal()
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self.submodules.bootstrap = GTPBootstrapClock(self.platform, clk_freq)
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self.submodules.sys_crg = zynq_clocking.SYSCRG(
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self.platform,
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self.ps7,
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txout_buf,
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clk_sw=gtx0.tx_init.done)
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clk_sw=self.gt_drtio.stable_clkin.storage,
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clk_sw_status=gtx0.tx_init.done,
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ext_async_rst=ext_async_rst)
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platform.add_false_path_constraints(
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self.bootstrap.cd_bootstrap.clk, self.sys_crg.cd_sys.clk)
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self.csr_devices.append("sys_crg")
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@ -433,6 +444,9 @@ class GenericSatellite(SoCCore):
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fix_serdes_timing_path(platform)
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self.comb += ext_async_rst.eq(self.sys_crg.clk_sw_fsm.o_clk_sw & ~gtx0.tx_init.done)
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self.specials += MultiReg(self.sys_crg.clk_sw_fsm.o_clk_sw & self.sys_crg.mmcm_locked, self.gt_drtio.clk_path_ready, odomain="bootstrap")
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self.rtio_channels = []
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has_grabber = any(peripheral["type"] == "grabber" for peripheral in description["peripherals"])
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if has_grabber:
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@ -226,6 +226,7 @@ class _MasterBase(SoCCore):
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self.csr_devices.append("gt_drtio")
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self.submodules.rtio_tsc = rtio.TSC(glbl_fine_ts_width=3)
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ext_async_rst = Signal()
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txout_buf = Signal()
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gtx0 = self.gt_drtio.gtxs[0]
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self.specials += Instance("BUFG", i_I=gtx0.txoutclk, o_O=txout_buf)
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@ -234,12 +235,17 @@ class _MasterBase(SoCCore):
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self.platform,
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self.ps7,
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txout_buf,
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clk_sw=gtx0.tx_init.done,
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clk_sw=self.gt_drtio.stable_clkin.storage,
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clk_sw_status=gtx0.tx_init.done,
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ext_async_rst=ext_async_rst,
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freq=clk_freq)
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platform.add_false_path_constraints(
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self.bootstrap.cd_bootstrap.clk, self.sys_crg.cd_sys.clk)
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self.csr_devices.append("sys_crg")
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self.comb += ext_async_rst.eq(self.sys_crg.clk_sw_fsm.o_clk_sw & ~gtx0.tx_init.done)
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self.specials += MultiReg(self.sys_crg.clk_sw_fsm.o_clk_sw & self.sys_crg.mmcm_locked, self.gt_drtio.clk_path_ready, odomain="bootstrap")
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drtio_csr_group = []
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drtioaux_csr_group = []
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drtioaux_memory_group = []
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@ -361,6 +367,7 @@ class _SatelliteBase(SoCCore):
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clk_freq=clk_freq)
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self.csr_devices.append("gt_drtio")
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ext_async_rst = Signal()
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txout_buf = Signal()
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txout_buf.attr.add("keep")
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gtx0 = self.gt_drtio.gtxs[0]
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@ -373,12 +380,17 @@ class _SatelliteBase(SoCCore):
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self.platform,
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self.ps7,
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txout_buf,
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clk_sw=gtx0.tx_init.done,
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clk_sw=self.gt_drtio.stable_clkin.storage,
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clk_sw_status=gtx0.tx_init.done,
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ext_async_rst=ext_async_rst,
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freq=clk_freq)
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platform.add_false_path_constraints(
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self.bootstrap.cd_bootstrap.clk, self.sys_crg.cd_sys.clk)
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self.csr_devices.append("sys_crg")
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self.comb += ext_async_rst.eq(self.sys_crg.clk_sw_fsm.o_clk_sw & ~gtx0.tx_init.done)
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self.specials += MultiReg(self.sys_crg.clk_sw_fsm.o_clk_sw & self.sys_crg.mmcm_locked, self.gt_drtio.clk_path_ready, odomain="bootstrap")
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drtioaux_csr_group = []
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drtioaux_memory_group = []
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drtiorep_csr_group = []
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@ -65,7 +65,7 @@ class ClockSwitchFSM(Module):
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class SYSCRG(Module, AutoCSR):
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def __init__(self, platform, ps7, main_clk, clk_sw=None, freq=125e6):
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def __init__(self, platform, ps7, main_clk, clk_sw=None, clk_sw_status=None, freq=125e6, ext_async_rst=None, ):
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# assumes bootstrap clock is same freq as main and sys output
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self.clock_domains.cd_sys = ClockDomain()
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self.clock_domains.cd_sys4x = ClockDomain(reset_less=True)
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@ -88,7 +88,7 @@ class SYSCRG(Module, AutoCSR):
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else:
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self.comb += self.clk_sw_fsm.i_clk_sw.eq(clk_sw)
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mmcm_locked = Signal()
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self.mmcm_locked = Signal()
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mmcm_sys = Signal()
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mmcm_sys4x = Signal()
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mmcm_sys5x = Signal()
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@ -96,7 +96,7 @@ class SYSCRG(Module, AutoCSR):
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mmcm_fb_clk = Signal()
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self.specials += [
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Instance("MMCME2_ADV",
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p_STARTUP_WAIT="FALSE", o_LOCKED=mmcm_locked,
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p_STARTUP_WAIT="FALSE", o_LOCKED=self.mmcm_locked,
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p_BANDWIDTH="HIGH",
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p_REF_JITTER1=0.001,
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p_CLKIN1_PERIOD=period, i_CLKIN1=main_clk,
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@ -125,10 +125,19 @@ class SYSCRG(Module, AutoCSR):
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Instance("BUFG", i_I=mmcm_sys, o_O=self.cd_sys.clk),
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Instance("BUFG", i_I=mmcm_sys4x, o_O=self.cd_sys4x.clk),
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Instance("BUFG", i_I=mmcm_clk208, o_O=self.cd_clk200.clk),
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AsyncResetSynchronizer(self.cd_sys, ~mmcm_locked),
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AsyncResetSynchronizer(self.cd_clk200, ~mmcm_locked),
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]
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if ext_async_rst is not None:
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self.specials += [
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AsyncResetSynchronizer(self.cd_sys, ~self.mmcm_locked | ext_async_rst),
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AsyncResetSynchronizer(self.cd_clk200, ~self.mmcm_locked | ext_async_rst),
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]
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else:
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self.specials += [
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AsyncResetSynchronizer(self.cd_sys, ~self.mmcm_locked),
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AsyncResetSynchronizer(self.cd_clk200, ~self.mmcm_locked),
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]
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reset_counter = Signal(4, reset=15)
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ic_reset = Signal(reset=1)
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self.sync.clk200 += \
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@ -139,4 +148,7 @@ class SYSCRG(Module, AutoCSR):
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)
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self.specials += Instance("IDELAYCTRL", i_REFCLK=ClockSignal("clk200"), i_RST=ic_reset)
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self.comb += self.current_clock.status.eq(self.clk_sw_fsm.o_clk_sw)
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if clk_sw_status is None:
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self.comb += self.current_clock.status.eq(self.clk_sw_fsm.o_clk_sw)
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else:
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self.comb += self.current_clock.status.eq(clk_sw_status)
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