szl: flush now write-buffered dcache of DDR pages before executing instructions in them

default.nix

@@ -15,7 +15,7 @@ let
       version = "0.1.0";
 
       src = ./src;
-      cargoSha256 = "13j5pkg4hvw85r38pi2faby4cl4zmhcfqncq68bnb738yfrmf91y";
+      cargoSha256 = "08y2dsnrn08mki9b0n336yanj7wpn5089kgc7l3jf9cwcjxqlhdj";
 
       nativeBuildInputs = [
         pkgs.gnumake

src/Cargo.lock

@@ -85,9 +85,9 @@ dependencies = [
 
 [[package]]
 name = "embedded-hal"
-version = "0.2.3"
+version = "0.2.4"
 source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "ee4908a155094da7723c2d60d617b820061e3b4efcc3d9e293d206a5a76c170b"
+checksum = "fa998ce59ec9765d15216393af37a58961ddcefb14c753b4816ba2191d865fcb"
 dependencies = [
  "nb",
  "void",
@@ -184,7 +184,7 @@ dependencies = [
 [[package]]
 name = "libasync"
 version = "0.0.0"
-source = "git+https://git.m-labs.hk/M-Labs/zc706.git#98f509968418d10dbc8198cb163cca774724111d"
+source = "git+https://git.m-labs.hk/M-Labs/zc706.git#b33ccf83ba13ea1370d82f309d318d8817f6db58"
 dependencies = [
  "embedded-hal",
  "libcortex_a9",
@@ -196,7 +196,7 @@ dependencies = [
 [[package]]
 name = "libboard_zynq"
 version = "0.0.0"
-source = "git+https://git.m-labs.hk/M-Labs/zc706.git#98f509968418d10dbc8198cb163cca774724111d"
+source = "git+https://git.m-labs.hk/M-Labs/zc706.git#b33ccf83ba13ea1370d82f309d318d8817f6db58"
 dependencies = [
  "bit_field",
  "embedded-hal",
@@ -212,7 +212,7 @@ dependencies = [
 [[package]]
 name = "libcortex_a9"
 version = "0.0.0"
-source = "git+https://git.m-labs.hk/M-Labs/zc706.git#98f509968418d10dbc8198cb163cca774724111d"
+source = "git+https://git.m-labs.hk/M-Labs/zc706.git#b33ccf83ba13ea1370d82f309d318d8817f6db58"
 dependencies = [
  "bit_field",
  "libregister",
@@ -221,7 +221,7 @@ dependencies = [
 [[package]]
 name = "libregister"
 version = "0.0.0"
-source = "git+https://git.m-labs.hk/M-Labs/zc706.git#98f509968418d10dbc8198cb163cca774724111d"
+source = "git+https://git.m-labs.hk/M-Labs/zc706.git#b33ccf83ba13ea1370d82f309d318d8817f6db58"
 dependencies = [
  "bit_field",
  "vcell",
@@ -231,7 +231,7 @@ dependencies = [
 [[package]]
 name = "libsupport_zynq"
 version = "0.0.0"
-source = "git+https://git.m-labs.hk/M-Labs/zc706.git#98f509968418d10dbc8198cb163cca774724111d"
+source = "git+https://git.m-labs.hk/M-Labs/zc706.git#b33ccf83ba13ea1370d82f309d318d8817f6db58"
 dependencies = [
  "compiler_builtins",
  "libboard_zynq",

src/szl/src/main.rs

@@ -7,6 +7,7 @@ use core::mem;
 use log::{info, error};
 use cstr_core::CStr;
 
+use libcortex_a9::cache::dcci_slice;
 use libboard_zynq::{
     self as zynq, clocks::Clocks, clocks::source::{ClockSource, ArmPll, IoPll},
     logger,
@@ -48,6 +49,12 @@ pub fn main_core0() {
     if result < 0 {
         error!("decompression failed");
     } else {
+        // Flush data cache entries for all of DDR, including
+        // Memory/Instruction Symchronization Barriers
+        dcci_slice(unsafe {
+            core::slice::from_raw_parts(ddr.ptr::<u8>(), ddr.size())
+        });
+
         // Start core0 only, for compatibility with FSBL.
         info!("executing payload");
         unsafe {