kasli_soc uses gtx transceiver instead of gtp

src/gateware/kasli_soc.py

@@ -16,7 +16,7 @@ from artiq.coredevice import jsondesc
 from artiq.gateware import rtio, eem_7series
 from artiq.gateware.rtio.phy import ttl_simple
 
-from artiq.gateware.drtio.transceiver import gtp_7series
+from artiq.gateware.drtio.transceiver import gtx_7series
 from artiq.gateware.drtio.siphaser import SiPhaser7Series
 from artiq.gateware.drtio.rx_synchronizer import XilinxRXSynchronizer
 from artiq.gateware.drtio import *
@@ -167,6 +167,9 @@ class GenericStandalone(SoCCore):
         
 class GenericMaster(SoCCore):
     mem_map = {
+        "cri_con":       0x10000000,
+        "rtio":          0x20000000,
+        "rtio_dma":      0x30000000,
         "drtioaux":      0x50000000
     }
     mem_map.update(SoCCore.mem_map)
@@ -193,11 +196,10 @@ class GenericMaster(SoCCore):
         # not sure yet why sfp0 is omitted in MasterMode
         drtio_data_pads = [platform.request("sfp", i) for i in range(4)]
 
-        self.submodules.drtio_transceiver = gtp_7series.GTP(
+        self.submodules.drtio_transceiver = gtx_7series.GTX(
-            qpll_channel=self.drtio_qpll_channel,  # todo figure out qpll
+            clock_pads=platform.request("clk125_gtp"),  # referred to as clk gtp in schematics, but for gtx?
             data_pads=drtio_data_pads,
-            sys_clk_freq=self.clk_freq,
+            sys_clk_freq=self.clk_freq)
-            rtio_clk_freq=rtio_clk_freq)
         self.csr_devices.append("drtio_transceiver")
         # todo figure out cdr lk clean
         # self.sync += self.disable_cdr_clk_ibuf.eq(
@@ -333,11 +335,10 @@ class GenericSatellite(SoCCore):
 
         drtio_data_pads = [platform.request("sfp", i) for i in range(4)]
 
-        self.submodules.drtio_transceiver = gtp_7series.GTP(
+        self.submodules.drtio_transceiver = gtx_7series.GTX(
-            qpll_channel=qpll.channels[0], # todo - figure out qpll
+            clock_pads=platform.request("clk125_gtp"),  # referred to as clk gtp in schematics, but for gtx?
             data_pads=drtio_data_pads,
-            sys_clk_freq=self.clk_freq,
+            sys_clk_freq=self.clk_freq)
-            rtio_clk_freq=rtio_clk_freq)
         self.csr_devices.append("drtio_transceiver")
         # same here - figure out the relations
         # self.sync += disable_cdr_clk_ibuf.eq(
@@ -429,11 +430,18 @@ class GenericSatellite(SoCCore):
         self.submodules.rtio_dma = dma.DMA(self.ps7.s_axi_hp0)
         self.csr_devices.append("rtio_dma")
 
+        self.submodules.local_io = SyncRTIO(self.rtio_tsc, rtio_channels)
+        self.comb += self.drtiosat.async_errors.eq(self.local_io.async_errors)
+
         self.submodules.cri_con = rtio.CRIInterconnectShared(
-            [self.rtio.cri, self.rtio_dma.cri],
+            [self.drtiosat.cri],
-            [self.rtio_core.cri])
+            [self.local_io.cri] + self.drtio_cri,
+            mode="sync", enable_routing=True)
         self.csr_devices.append("cri_con")
 
+        self.submodules.routing_table = rtio.RoutingTableAccess(self.cri_con)
+        self.csr_devices.append("routing_table")     
+
         self.submodules.rtio_moninj = rtio.MonInj(self.rtio_channels)
         self.csr_devices.append("rtio_moninj")
 
@@ -441,6 +449,9 @@ class GenericSatellite(SoCCore):
                                                           self.ps7.s_axi_hp1)
         self.csr_devices.append("rtio_analyzer")
 
+        rtio_clk_period = 1e9/rtio_clk_freq
+        self.config["RTIO_FREQUENCY"] = str(rtio_clk_freq/1e6)
+
         self.submodules.siphaser = SiPhaser7Series(
             si5324_clkin=platform.request("cdr_clk"),
             rx_synchronizer=self.rx_synchronizer,
@@ -452,6 +463,17 @@ class GenericSatellite(SoCCore):
         self.config["HAS_SI5324"] = None
         self.config["SI5324_SOFT_RESET"] = None
 
+        gtx = self.drtio_transceiver.gtps[0]
+        platform.add_period_constraint(gtx.txoutclk, rtio_clk_period)
+        platform.add_period_constraint(gtx.rxoutclk, rtio_clk_period)
+        platform.add_false_path_constraints(
+            self.crg.cd_sys.clk,
+            gtx.txoutclk, gtx.rxoutclk)
+        for gtx in self.drtio_transceiver.gtxs[1:]:
+            platform.add_period_constraint(gtx.rxoutclk, rtio_clk_period)
+            platform.add_false_path_constraints(
+                self.crg.cd_sys.clk, gtx.rxoutclk)
+
         if has_grabber:
             self.rustc_cfg["has_grabber"] = None
             self.add_csr_group("grabber", self.grabber_csr_group)

src/gateware/zc706.py

@@ -15,6 +15,11 @@ from misoc.integration import cpu_interface
 from artiq.gateware import rtio, nist_clock, nist_qc2
 from artiq.gateware.rtio.phy import ttl_simple, ttl_serdes_7series, dds, spi2
 
+from artiq.gateware.drtio.transceiver import gtx_7series
+from artiq.gateware.drtio.siphaser import SiPhaser7Series
+from artiq.gateware.drtio.rx_synchronizer import XilinxRXSynchronizer
+from artiq.gateware.drtio import *
+
 import dma
 import analyzer
 import acpki
@@ -121,6 +126,49 @@ class ZC706(SoCCore):
                                                           self.ps7.s_axi_hp1)
         self.csr_devices.append("rtio_analyzer")
 
+    def add_drtio(self):
+        platform = self.platform
+
+
+
+        drtio_csr_group = []
+        drtioaux_csr_group = []
+        drtioaux_memory_group = []
+        drtio_cri = []
+
+        for i in range(len(self.drtio_transceiver.channels)):
+            core_name = "drtio" + str(i)
+            coreaux_name = "drtioaux" + str(i)
+            memory_name = "drtioaux" + str(i) + "_mem"
+            drtio_csr_group.append(core_name)
+            drtioaux_csr_group.append(coreaux_name)
+            drtioaux_memory_group.append(memory_name)
+
+            cdr = ClockDomainsRenamer({"rtio_rx": "rtio_rx" + str(i)})
+
+            core = cdr(DRTIOMaster(
+                self.rtio_tsc, self.drtio_transceiver.channels[i]))
+            setattr(self.submodules, core_name, core)
+            drtio_cri.append(core.cri)
+            self.csr_devices.append(core_name)
+
+            coreaux = cdr(DRTIOAuxController(core.link_layer))
+            setattr(self.submodules, coreaux_name, coreaux)
+            self.csr_devices.append(coreaux_name)
+
+            memory_address = self.mem_map["drtioaux"] + 0x800*i
+            self.add_wb_slave(memory_address, 0x800,
+                              coreaux.bus)
+            self.add_memory_region(memory_name, memory_address | self.shadow_base, 0x800)
+        
+        self.rustc_cfg["HAS_DRTIO"] = None
+        self.rustc_cfg["HAS_DRTIO_ROUTING"] = None
+        self.add_csr_group("drtio", drtio_csr_group)
+        self.add_csr_group("drtioaux", drtioaux_csr_group)
+        self.add_memory_group("drtioaux_mem", drtioaux_memory_group)
+
+
+
 
 class Simple(ZC706):
     def __init__(self, **kwargs):
@@ -252,8 +300,265 @@ class NIST_QC2(ZC706):
 
         self.add_rtio(rtio_channels)
 
+class Master(ZC706):
+    mem_map = {
+        "cri_con":      0x10000000,
+        "rtio":         0x20000000,
+        "rtio_dma":     0x30000000,
+        "drtioaux":     0x50000000,
+    }
+    mem_map.update(BaseSoC.mem_map)
 
-VARIANTS = {cls.__name__.lower(): cls for cls in [Simple, NIST_CLOCK, NIST_QC2]}
+    def __init__(self, **kwargs):
+        ZC706.__init__(self, **kwargs)
+
+        platform = self.platform
+
+        self.comb += platform.request("sfp_tx_disable_n").eq(1)
+        tx_pads = [
+            platform.request("sfp_tx"), platform.request("user_sma_mgt_tx")
+        ]
+        rx_pads = [
+            platform.request("sfp_rx"), platform.request("user_sma_mgt_rx")
+        ]
+
+        # 1000BASE_BX10 Ethernet compatible, 125MHz RTIO clock
+        self.submodules.drtio_transceiver = gtx_7series.GTX(
+            clock_pads=platform.request("si5324_clkout"),
+            tx_pads=tx_pads,
+            rx_pads=rx_pads,
+            sys_clk_freq=self.clk_freq)
+        self.csr_devices.append("drtio_transceiver")
+
+        self.submodules.rtio_tsc = rtio.TSC("async", glbl_fine_ts_width=3)
+
+        drtio_csr_group = []
+        drtioaux_csr_group = []
+        drtioaux_memory_group = []
+        drtio_cri = []
+        for i in range(len(self.drtio_transceiver.channels)):
+            core_name = "drtio" + str(i)
+            coreaux_name = "drtioaux" + str(i)
+            memory_name = "drtioaux" + str(i) + "_mem"
+            drtio_csr_group.append(core_name)
+            drtioaux_csr_group.append(coreaux_name)
+            drtioaux_memory_group.append(memory_name)
+
+            cdr = ClockDomainsRenamer({"rtio_rx": "rtio_rx" + str(i)})
+
+            core = cdr(DRTIOMaster(
+                self.rtio_tsc, self.drtio_transceiver.channels[i]))
+            setattr(self.submodules, core_name, core)
+            drtio_cri.append(core.cri)
+            self.csr_devices.append(core_name)
+
+            coreaux = cdr(DRTIOAuxController(core.link_layer))
+            setattr(self.submodules, coreaux_name, coreaux)
+            self.csr_devices.append(coreaux_name)
+
+            memory_address = self.mem_map["drtioaux"] + 0x800*i
+            self.add_wb_slave(memory_address, 0x800,
+                              coreaux.bus)
+            self.add_memory_region(memory_name, memory_address | self.shadow_base, 0x800)
+        self.config["HAS_DRTIO"] = None
+        self.config["HAS_DRTIO_ROUTING"] = None
+        self.add_csr_group("drtio", drtio_csr_group)
+        self.add_csr_group("drtioaux", drtioaux_csr_group)
+        self.add_memory_group("drtioaux_mem", drtioaux_memory_group)
+
+        self.config["RTIO_FREQUENCY"] = str(self.drtio_transceiver.rtio_clk_freq/1e6)
+        self.submodules.si5324_rst_n = gpio.GPIOOut(platform.request("si5324").rst_n)
+        self.csr_devices.append("si5324_rst_n")
+        # i2c not supported? todo - figure out if it should be
+        self.config["HAS_SI5324"] = None
+        self.config["SI5324_AS_SYNTHESIZER"] = None
+
+        user_sma_clock = platform.request("user_sma_clock")
+        self.comb += [
+            user_sma_clock.p.eq(ClockSignal("rtio_rx0")),
+            user_sma_clock.n.eq(ClockSignal("rtio"))
+        ]
+
+        rtio_clk_period = 1e9/self.drtio_transceiver.rtio_clk_freq
+        # Constrain TX & RX timing for the first transceiver channel
+        # (First channel acts as master for phase alignment for all channels' TX)
+        gtx0 = self.drtio_transceiver.gtxs[0]
+        platform.add_period_constraint(gtx0.txoutclk, rtio_clk_period)
+        platform.add_period_constraint(gtx0.rxoutclk, rtio_clk_period)
+        platform.add_false_path_constraints(
+            self.crg.cd_sys.clk,
+            gtx0.txoutclk, gtx0.rxoutclk)
+        # Constrain RX timing for the each transceiver channel
+        # (Each channel performs single-lane phase alignment for RX)
+        for gtx in self.drtio_transceiver.gtxs[1:]:
+            platform.add_period_constraint(gtx.rxoutclk, rtio_clk_period)
+            platform.add_false_path_constraints(
+                self.crg.cd_sys.clk, gtx0.txoutclk, gtx.rxoutclk)
+
+        rtio_channels = []
+        for i in range(4):
+            phy = ttl_simple.Output(platform.request("user_led", i))
+            self.submodules += phy
+            rtio_channels.append(rtio.Channel.from_phy(phy))
+
+        self.config["RTIO_LOG_CHANNEL"] = len(rtio_channels)
+        rtio_channels.append(rtio.LogChannel())
+
+        self.add_rtio(rtio_channels)
+
+class Satellite(ZC706):
+    def __init__(self, **kwargs):
+        ZC706.__init__(self, **kwargs)
+
+        platform = self.platform
+
+        self.comb += platform.request("sfp_tx_disable_n").eq(1)
+        tx_pads = [
+            platform.request("sfp_tx")
+        ]
+        rx_pads = [
+            platform.request("sfp_rx")
+        ]
+
+        # 1000BASE_BX10 Ethernet compatible, 125MHz RTIO clock
+        self.submodules.drtio_transceiver = gtx_7series.GTX(
+            clock_pads=platform.request("si5324_clkout"),
+            tx_pads=tx_pads,
+            rx_pads=rx_pads,
+            sys_clk_freq=self.clk_freq)
+        self.csr_devices.append("drtio_transceiver")
+
+        self.submodules.rtio_tsc = rtio.TSC("sync", glbl_fine_ts_width=3)
+
+        drtioaux_csr_group = []
+        drtioaux_memory_group = []
+        drtiorep_csr_group = []
+        self.drtio_cri = []
+        for i in range(len(self.drtio_transceiver.channels)):
+            coreaux_name = "drtioaux" + str(i)
+            memory_name = "drtioaux" + str(i) + "_mem"
+            drtioaux_csr_group.append(coreaux_name)
+            drtioaux_memory_group.append(memory_name)
+
+            cdr = ClockDomainsRenamer({"rtio_rx": "rtio_rx" + str(i)})
+
+            # Satellite
+            if i == 0:
+                self.submodules.rx_synchronizer = cdr(XilinxRXSynchronizer())
+                core = cdr(DRTIOSatellite(
+                    self.rtio_tsc, self.drtio_transceiver.channels[0], self.rx_synchronizer))
+                self.submodules.drtiosat = core
+                self.csr_devices.append("drtiosat")
+            # Repeaters
+            else:
+                corerep_name = "drtiorep" + str(i-1)
+                drtiorep_csr_group.append(corerep_name)
+                core = cdr(DRTIORepeater(
+                    self.rtio_tsc, self.drtio_transceiver.channels[i]))
+                setattr(self.submodules, corerep_name, core)
+                self.drtio_cri.append(core.cri)
+                self.csr_devices.append(corerep_name)
+
+            coreaux = cdr(DRTIOAuxController(core.link_layer))
+            setattr(self.submodules, coreaux_name, coreaux)
+            self.csr_devices.append(coreaux_name)
+
+            memory_address = self.mem_map["drtioaux"] + 0x800*i
+            self.add_wb_slave(memory_address, 0x800,
+                              coreaux.bus)
+            self.add_memory_region(memory_name, memory_address | self.shadow_base, 0x800)
+        self.config["HAS_DRTIO"] = None
+        self.config["HAS_DRTIO_ROUTING"] = None
+        self.add_csr_group("drtioaux", drtioaux_csr_group)
+        self.add_memory_group("drtioaux_mem", drtioaux_memory_group)
+        self.add_csr_group("drtiorep", drtiorep_csr_group)
+
+        self.config["RTIO_FREQUENCY"] = str(self.drtio_transceiver.rtio_clk_freq/1e6)
+
+        # Si5324 Phaser
+        self.submodules.siphaser = SiPhaser7Series(
+            si5324_clkin=platform.request("si5324_clkin"),
+            rx_synchronizer=self.rx_synchronizer,
+            ultrascale=False,
+            rtio_clk_freq=self.drtio_transceiver.rtio_clk_freq)
+        platform.add_false_path_constraints(
+            self.crg.cd_sys.clk, self.siphaser.mmcm_freerun_output)
+        self.csr_devices.append("siphaser")
+        self.submodules.si5324_rst_n = gpio.GPIOOut(platform.request("si5324").rst_n)
+        self.csr_devices.append("si5324_rst_n")
+        i2c = self.platform.request("i2c")
+        self.submodules.i2c = gpio.GPIOTristate([i2c.scl, i2c.sda])
+        self.csr_devices.append("i2c")
+        self.config["I2C_BUS_COUNT"] = 1
+        self.config["HAS_SI5324"] = None
+
+        user_sma_clock = platform.request("user_sma_clock")
+        self.comb += [
+            user_sma_clock.p.eq(ClockSignal("rtio_rx0")),
+            user_sma_clock.n.eq(ClockSignal("rtio"))
+        ]
+
+        rtio_clk_period = 1e9/self.drtio_transceiver.rtio_clk_freq
+        # Constrain TX & RX timing for the first transceiver channel
+        # (First channel acts as master for phase alignment for all channels' TX)
+        gtx0 = self.drtio_transceiver.gtxs[0]
+        platform.add_period_constraint(gtx0.txoutclk, rtio_clk_period)
+        platform.add_period_constraint(gtx0.rxoutclk, rtio_clk_period)
+        platform.add_false_path_constraints(
+            self.crg.cd_sys.clk,
+            gtx0.txoutclk, gtx0.rxoutclk)
+        # Constrain RX timing for the each transceiver channel
+        # (Each channel performs single-lane phase alignment for RX)
+        for gtx in self.drtio_transceiver.gtxs[1:]:
+            platform.add_period_constraint(gtx.rxoutclk, rtio_clk_period)
+            platform.add_false_path_constraints(
+                self.crg.cd_sys.clk, gtx.rxoutclk)
+
+        rtio_channels = []
+        for i in range(4):
+            phy = ttl_simple.Output(platform.request("user_led", i))
+            self.submodules += phy
+            rtio_channels.append(rtio.Channel.from_phy(phy))
+
+        self.config["RTIO_LOG_CHANNEL"] = len(rtio_channels)
+        rtio_channels.append(rtio.LogChannel())
+
+        self.add_rtio(rtio_channels)
+
+    def add_rtio(self, rtio_channels):
+        # few changes from base add_rtio - moved tsc, no core
+        self.submodules.rtio_core = rtio.Core(self.rtio_tsc, rtio_channels)
+
+        if self.acpki:
+            self.rustc_cfg["ki_impl"] = "acp"
+            self.submodules.rtio = acpki.KernelInitiator(self.rtio_tsc,
+                                                         bus=self.ps7.s_axi_acp,
+                                                         user=self.ps7.s_axi_acp_user,
+                                                         evento=self.ps7.event.o)
+            self.csr_devices.append("rtio")
+        else:
+            self.rustc_cfg["ki_impl"] = "csr"
+            self.submodules.rtio = rtio.KernelInitiator(self.rtio_tsc, now64=True)
+            self.csr_devices.append("rtio")
+
+        self.submodules.cri_con = rtio.CRIInterconnectShared(
+            [self.drtiosat.cri],
+            [self.local_io.cri] + self.drtio_cri,
+            mode="sync", enable_routing=True)
+        self.csr_devices.append("cri_con")
+
+        self.submodules.routing_table = rtio.RoutingTableAccess(self.cri_con)
+        self.csr_devices.append("routing_table")
+
+        self.submodules.rtio_moninj = rtio.MonInj(rtio_channels)
+        self.csr_devices.append("rtio_moninj")
+
+        self.submodules.rtio_analyzer = analyzer.Analyzer(self.rtio_tsc, self.rtio_core.cri,
+                                                          self.ps7.s_axi_hp1)
+        self.csr_devices.append("rtio_analyzer")
+
+
+VARIANTS = {cls.__name__.lower(): cls for cls in [Simple, NIST_CLOCK, NIST_QC2, Master, Satellite]}
 
 
 def write_csr_file(soc, filename):