add has_rtio_moninj cfg to zc706 satellite

Co-authored-by: morgan <mc@m-labs.hk>
Co-committed-by: morgan <mc@m-labs.hk>

src/gateware/zc706.py

@@ -142,6 +142,7 @@ def prepare_zc706_platform(platform):
 class ZC706(SoCCore):
     def __init__(self, acpki=False):
         self.acpki = acpki
+        self.rustc_cfg = dict()
 
         platform = zc706.Platform()
         prepare_zc706_platform(platform)
@@ -153,7 +154,7 @@ class ZC706(SoCCore):
 
         self.submodules.rtio_crg = RTIOCRG(self.platform, self.ps7.cd_sys.clk)
         self.csr_devices.append("rtio_crg")
-        self.config["has_rtio_crg_clock_sel"] = None
+        self.rustc_cfg["has_rtio_crg_clock_sel"] = None
         self.platform.add_period_constraint(self.rtio_crg.cd_rtio.clk, 8.)
         self.platform.add_false_path_constraints(
             self.ps7.cd_sys.clk,
@@ -165,14 +166,14 @@ class ZC706(SoCCore):
         self.csr_devices.append("rtio_core")
 
         if self.acpki:
-            self.config["ki_impl"] = "acp"
+            self.rustc_cfg["ki_impl"] = "acp"
             self.submodules.rtio = acpki.KernelInitiator(self.rtio_tsc,
                                                          bus=self.ps7.s_axi_acp,
                                                          user=self.ps7.s_axi_acp_user,
                                                          evento=self.ps7.event.o)
             self.csr_devices.append("rtio")
         else:
-            self.config["ki_impl"] = "csr"
+            self.rustc_cfg["ki_impl"] = "csr"
             self.submodules.rtio = rtio.KernelInitiator(self.rtio_tsc, now64=True)
             self.csr_devices.append("rtio")
 
@@ -195,6 +196,7 @@ class ZC706(SoCCore):
 class _MasterBase(SoCCore):
     def __init__(self, acpki=False, drtio100mhz=False):
         self.acpki = acpki
+        self.rustc_cfg = dict()
 
         platform = zc706.Platform()
         prepare_zc706_platform(platform)
@@ -256,18 +258,18 @@ class _MasterBase(SoCCore):
             memory_address = self.axi2csr.register_port(coreaux.get_tx_port(), mem_size)
             self.axi2csr.register_port(coreaux.get_rx_port(), mem_size)
             self.add_memory_region(memory_name, self.mem_map["csr"] + memory_address, mem_size * 2)
-        self.config["has_drtio"] = None
-        self.config["has_drtio_routing"] = None
+        self.rustc_cfg["has_drtio"] = None
+        self.rustc_cfg["has_drtio_routing"] = None
         self.add_csr_group("drtio", drtio_csr_group)
         self.add_csr_group("drtioaux", drtioaux_csr_group)
         self.add_memory_group("drtioaux_mem", drtioaux_memory_group)
 
-        self.config["rtio_frequency"] = str(self.drtio_transceiver.rtio_clk_freq/1e6)
+        self.rustc_cfg["rtio_frequency"] = str(self.drtio_transceiver.rtio_clk_freq/1e6)
 
         self.submodules.si5324_rst_n = gpio.GPIOOut(platform.request("si5324_33").rst_n)
         self.csr_devices.append("si5324_rst_n")
-        self.config["has_si5324"] = None
-        self.config["si5324_as_synthesizer"] = None
+        self.rustc_cfg["has_si5324"] = None
+        self.rustc_cfg["si5324_as_synthesizer"] = None
 
         rtio_clk_period = 1e9/self.drtio_transceiver.rtio_clk_freq
         # Constrain TX & RX timing for the first transceiver channel
@@ -295,14 +297,14 @@ class _MasterBase(SoCCore):
         self.csr_devices.append("rtio_core")
 
         if self.acpki:
-            self.config["ki_impl"] = "acp"
+            self.rustc_cfg["ki_impl"] = "acp"
             self.submodules.rtio = acpki.KernelInitiator(self.rtio_tsc,
                                                          bus=self.ps7.s_axi_acp,
                                                          user=self.ps7.s_axi_acp_user,
                                                          evento=self.ps7.event.o)
             self.csr_devices.append("rtio")
         else:
-            self.config["ki_impl"] = "csr"
+            self.rustc_cfg["ki_impl"] = "csr"
             self.submodules.rtio = rtio.KernelInitiator(self.rtio_tsc, now64=True)
             self.csr_devices.append("rtio")
 
@@ -329,6 +331,7 @@ class _MasterBase(SoCCore):
 class _SatelliteBase(SoCCore):
     def __init__(self, acpki=False, drtio100mhz=False):
         self.acpki = acpki
+        self.rustc_cfg = dict()
 
         platform = zc706.Platform()
         prepare_zc706_platform(platform)
@@ -402,13 +405,13 @@ class _SatelliteBase(SoCCore):
             # and registered in PS interface
             # manually, because software refers to rx/tx by halves of entire memory block, not names
             self.add_memory_region(memory_name, self.mem_map["csr"] + memory_address, mem_size * 2)
-        self.config["has_drtio"] = None
-        self.config["has_drtio_routing"] = None
+        self.rustc_cfg["has_drtio"] = None
+        self.rustc_cfg["has_drtio_routing"] = None
         self.add_csr_group("drtioaux", drtioaux_csr_group)
         self.add_csr_group("drtiorep", drtiorep_csr_group)
         self.add_memory_group("drtioaux_mem", drtioaux_memory_group)
 
-        self.config["rtio_frequency"] = str(self.drtio_transceiver.rtio_clk_freq/1e6)
+        self.rustc_cfg["rtio_frequency"] = str(self.drtio_transceiver.rtio_clk_freq/1e6)
 
         # Si5324 Phaser
         self.submodules.siphaser = SiPhaser7Series(
@@ -421,8 +424,8 @@ class _SatelliteBase(SoCCore):
         self.csr_devices.append("siphaser")
         self.submodules.si5324_rst_n = gpio.GPIOOut(platform.request("si5324_33").rst_n)
         self.csr_devices.append("si5324_rst_n")
-        self.config["has_si5324"] = None
-        self.config["has_siphaser"] = None
+        self.rustc_cfg["has_si5324"] = None
+        self.rustc_cfg["has_siphaser"] = None
 
         rtio_clk_period = 1e9/self.drtio_transceiver.rtio_clk_freq
         # Constrain TX & RX timing for the first transceiver channel
@@ -442,22 +445,23 @@ class _SatelliteBase(SoCCore):
 
         self.submodules.rtio_crg = RTIOClockMultiplier(self.sys_clk_freq)
         self.csr_devices.append("rtio_crg")
-        self.config["has_rtio_crg"] = None
+        self.rustc_cfg["has_rtio_crg"] = None
         fix_serdes_timing_path(self.platform)
 
     def add_rtio(self, rtio_channels):
         self.submodules.rtio_moninj = rtio.MonInj(rtio_channels)
         self.csr_devices.append("rtio_moninj")
+        self.rustc_cfg["has_rtio_moninj"] = None
 
         if self.acpki:
-            self.config["ki_impl"] = "acp"
+            self.rustc_cfg["ki_impl"] = "acp"
             self.submodules.rtio = acpki.KernelInitiator(self.rtio_tsc,
                                                          bus=self.ps7.s_axi_acp,
                                                          user=self.ps7.s_axi_acp_user,
                                                          evento=self.ps7.event.o)
             self.csr_devices.append("rtio")
         else:
-            self.config["ki_impl"] = "csr"
+            self.rustc_cfg["ki_impl"] = "csr"
             self.submodules.rtio = rtio.KernelInitiator(self.rtio_tsc, now64=True)
             self.csr_devices.append("rtio")
 
@@ -666,14 +670,11 @@ def write_mem_file(soc, filename):
 
 def write_rustc_cfg_file(soc, filename):
     with open(filename, "w") as f:
-        for name, origin, busword, obj in soc.get_csr_regions():
-            f.write("has_{}\n".format(name.lower()))
-        for name, value in soc.get_constants():
-            if name.upper().startswith("CONFIG_"):
-                if value is None:
-                    f.write("{}\n".format(name.lower()[7:]))
-                else:
-                    f.write("{}=\"{}\"\n".format(name.lower()[7:], str(value)))
+        for k, v in sorted(soc.rustc_cfg.items(), key=itemgetter(0)):
+            if v is None:
+                f.write("{}\n".format(k))
+            else:
+                f.write("{}=\"{}\"\n".format(k, v))
 
 
 def main():

src/runtime/src/main.rs

@@ -11,6 +11,7 @@
 
 extern crate alloc;
 
+#[cfg(feature = "target_kasli_soc")]
 use core::cell::RefCell;
 use log::{info, warn, error};
 
@@ -148,14 +149,11 @@ pub fn main_core0() {
     info!("gateware ident: {}", identifier_read(&mut [0; 64]));
 
     i2c::init();
-    let i2c_bus = unsafe { (i2c::I2C_BUS).as_mut().unwrap() };
-
-    #[cfg(feature = "target_kasli_soc")]
-    let (mut io_expander0, mut io_expander1);
     #[cfg(feature = "target_kasli_soc")]
     {
-        io_expander0 = io_expander::IoExpander::new(i2c_bus, 0).unwrap();
-        io_expander1 = io_expander::IoExpander::new(i2c_bus, 1).unwrap();
+        let i2c_bus = unsafe { (i2c::I2C_BUS).as_mut().unwrap() };
+        let mut io_expander0 = io_expander::IoExpander::new(i2c_bus, 0).unwrap();
+        let mut io_expander1 = io_expander::IoExpander::new(i2c_bus, 1).unwrap();
         io_expander0
             .init(i2c_bus)
             .expect("I2C I/O expander #0 initialization failed");
@@ -169,6 +167,11 @@ pub fn main_core0() {
         io_expander1.set(1, 1, false);
         io_expander0.service(i2c_bus).unwrap();
         io_expander1.service(i2c_bus).unwrap();
+        task::spawn(io_expanders_service(
+            RefCell::new(i2c_bus),
+            RefCell::new(io_expander0),
+            RefCell::new(io_expander1),
+        ));
     }
 
     let cfg = match Config::new() {
@@ -186,11 +189,5 @@ pub fn main_core0() {
     #[cfg(has_grabber)]
     task::spawn(grabber::grabber_thread(timer));
 
-    #[cfg(feature = "target_kasli_soc")]
-    task::spawn(io_expanders_service(
-        RefCell::new(i2c_bus),
-        RefCell::new(io_expander0),
-        RefCell::new(io_expander1),
-    ));
     comms::main(timer, cfg);
 }

src/runtime/src/rtio_acp.rs

@@ -11,6 +11,7 @@ pub const RTIO_O_STATUS_UNDERFLOW:                 i32 = 2;
 pub const RTIO_O_STATUS_DESTINATION_UNREACHABLE:   i32 = 4;
 pub const RTIO_I_STATUS_WAIT_EVENT:                i32 = 1;
 pub const RTIO_I_STATUS_OVERFLOW:                  i32 = 2;
+#[allow(unused)]
 pub const RTIO_I_STATUS_WAIT_STATUS:               i32 = 4; // TODO
 pub const RTIO_I_STATUS_DESTINATION_UNREACHABLE:   i32 = 8;