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M-Labs:release-7
M-Labs:release-6
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compare: M-Labs:8fd524d36bb47d82061fe19367ca86e57f3fdc28
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M-Labs:release-7
M-Labs:release-6

6 Commits
005f96a924 ... 8fd524d36b

Author SHA1 Message Date
morgan 8fd524d36b Firmware: Runtime WRPLL 
runtime: drive CLK_SEL to true when si549 is used
runtime & libboard_artiq: allow standalone to use io_expander
si549: add bit bang mmcm dynamic configuration
si549: add frequency counter for refclk
rtio_clocking & si549: add 125Mhz wrpll refclk setup
 2024-03-26 11:47:48 +08:00
morgan e5aad47cb2 Firmware: Satman skew calibration & tester 
cargo template: add calibrate_wrpll_skew feature
tag collector: add TAG_OFFSET for Satman WRPLL
tag collector: add TAG_OFFSET getter & setter for calibration
wrpll: add skew tester and calibration
wrpll: gate calibration behind calibrate_wrpll_skew feature
 2024-03-26 11:47:48 +08:00
morgan 07b7ea04d4 Firmware: Satman WRPLL 
satman: drive CLK_SEL to true when si549 is used
satman : add main & helper si549 setup
satman : add WRPLL select_recovered_clock
si549: add tag collector to process gtx & main tags
si549: add frequency counter to set BASE_ADPLL
si549: add set_adpll for main & helper PLL
si549: add main & helper PLL
FIQ & si549: replace dummy with a custom handler for gtx & main tags ISR
 2024-03-26 11:47:48 +08:00
morgan a9ed4aa180 Firmware: Si549 and io_expander 
io_expander: set CLK_SEL pin to output when si549 is used
io_expander: gate virtual leds for standalone
si549: add bit bang i2c
si549: add si549 programming
si549: add main & helper setup
 2024-03-26 11:47:47 +08:00
morgan 68a11bf7a3 Gateware: kasli_soc WRPLL setup 
kasli_soc: use enable_wrpll from json to switch from si5324 to si549
kasli_soc: add wrpll for all variants
kasli_soc: add gtx & main tag nFIQ for all variants
kasli_soc: add wrpll_refclk for runtime
kasli_soc: add skewtester for satman
kasli_soc: add WRPLL_REF_CLK config for firmware
 2024-03-26 11:47:40 +08:00
morgan 530fb2e7b0 Gateware: WRPLL 
ddmtd: add DDMTD and deglitcher
wrpll: add helper clockdomain
wrpll: add frequency counter
wrpll: add skewtester
wrpll: add gtx & main tag collection
wrpll: add gtx & main tag eventmanager for shared peripheral interrupt
wrpll: add SMA frequency multiplier to generate 125Mhz refclk
si549: add i2c and adpll programmer
 2024-03-26 10:10:06 +08:00
1 changed files with 19 additions and 21 deletions
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40
src/gateware/kasli_soc.py
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@ -48,19 +48,6 @@ eem_iostandard_dict = {
def eem_iostandard(eem):
return IOStandard(eem_iostandard_dict[eem])
class ClockSynthesis(Module):
def __init__(self, platform):
self.se = Signal()
clk_synth = platform.request("cdr_clk_clean_fabric")
platform.add_period_constraint(clk_synth.p, 8.0)
self.specials += [
Instance("IBUFGDS",
p_DIFF_TERM="TRUE", p_IBUF_LOW_PWR="FALSE",
i_I=clk_synth.p, i_IB=clk_synth.n, o_O=self.se
),
]
class SMAClkinForward(Module):
def __init__(self, platform):
@ -134,11 +121,18 @@ class GenericStandalone(SoCCore):
SoCCore.__init__(self, platform=platform, csr_data_width=32, ident=ident, ps_cd_sys=False)
self.config["HW_REV"] = description["hw_rev"]
self.submodules.clk_synth = ClockSynthesis(self.platform)
clk_synth = platform.request("cdr_clk_clean_fabric")
clk_synth_se = Signal()
clk_synth_se_buf = Signal()
self.specials += Instance("BUFG", i_I=self.clk_synth.se, o_O=clk_synth_se_buf)
platform.add_period_constraint(clk_synth.p, 8.0)
self.specials += [
Instance("IBUFGDS",
p_DIFF_TERM="TRUE", p_IBUF_LOW_PWR="FALSE",
i_I=clk_synth.p, i_IB=clk_synth.n, o_O=clk_synth_se
),
Instance("BUFG", i_I=clk_synth_se, o_O=clk_synth_se_buf),
]
fix_serdes_timing_path(platform)
self.submodules.bootstrap = GTPBootstrapClock(self.platform, clk_freq)
self.config["CLOCK_FREQUENCY"] = int(clk_freq)
@ -155,7 +149,7 @@ class GenericStandalone(SoCCore):
self.submodules.wrpll = wrpll.WRPLL(
platform=self.platform,
cd_ref=self.wrpll_refclk.cd_ref,
main_clk_se=self.clk_synth.se)
main_clk_se=clk_synth_se)
self.csr_devices.append("wrpll_refclk")
self.csr_devices.append("wrpll")
self.comb += self.ps7.core.core0.nfiq.eq(self.wrpll.ev.irq)
@ -275,12 +269,14 @@ class GenericMaster(SoCCore):
self.specials += MultiReg(self.sys_crg.clk_sw_fsm.o_clk_sw & self.sys_crg.mmcm_locked, self.gt_drtio.clk_path_ready, odomain="bootstrap")
if with_wrpll:
self.submodules.clk_synth = ClockSynthesis(self.platform)
clk_synth = platform.request("cdr_clk_clean_fabric")
clk_synth_se = Signal()
self.specials += Instance("IBUFGDS", p_DIFF_TERM="TRUE", p_IBUF_LOW_PWR="FALSE", i_I=clk_synth.p, i_IB=clk_synth.n, o_O=clk_synth_se)
self.submodules.wrpll_refclk = wrpll.SMAFrequencyMultiplier(platform.request("sma_clkin"))
self.submodules.wrpll = wrpll.WRPLL(
platform=self.platform,
cd_ref=self.wrpll_refclk.cd_ref,
main_clk_se=self.clk_synth.se)
main_clk_se=clk_synth_se)
self.csr_devices.append("wrpll_refclk")
self.csr_devices.append("wrpll")
self.comb += self.ps7.core.core0.nfiq.eq(self.wrpll.ev.irq)
@ -584,11 +580,13 @@ class GenericSatellite(SoCCore):
self.config["CLOCK_FREQUENCY"] = int(clk_freq)
if with_wrpll:
self.submodules.clk_synth = ClockSynthesis(self.platform)
clk_synth = platform.request("cdr_clk_clean_fabric")
clk_synth_se = Signal()
self.specials += Instance("IBUFGDS", p_DIFF_TERM="TRUE", p_IBUF_LOW_PWR="FALSE", i_I=clk_synth.p, i_IB=clk_synth.n, o_O=clk_synth_se)
self.submodules.wrpll = wrpll.WRPLL(
platform=self.platform,
cd_ref=self.gt_drtio.cd_rtio_rx0,
main_clk_se=self.clk_synth.se)
main_clk_se=clk_synth_se)
self.submodules.wrpll_skewtester = wrpll.SkewTester(self.rx_synchronizer)
self.csr_devices.append("wrpll_skewtester")
self.csr_devices.append("wrpll")