From fc7520bc63bdcd886dec3bb8f38eeeb051ecda7b Mon Sep 17 00:00:00 2001
From: mwojcik <mw@m-labs.hk>
Date: Thu, 28 Oct 2021 16:54:53 +0800
Subject: [PATCH] rtio_clocking: added si5324 settings from mainline

---
 src/runtime/src/rtio_clocking.rs | 65 ++++++++++++++++++++++++++++++++
 1 file changed, 65 insertions(+)

diff --git a/src/runtime/src/rtio_clocking.rs b/src/runtime/src/rtio_clocking.rs
index 93869f4..566107f 100644
--- a/src/runtime/src/rtio_clocking.rs
+++ b/src/runtime/src/rtio_clocking.rs
@@ -103,6 +103,71 @@ fn init_drtio(timer: &mut GlobalTimer)
 #[cfg(has_si5324)]
 fn setup_si5324(i2c: &mut I2c, timer: &mut GlobalTimer, clk: RtioClock) {
     let si5324_settings = match clk {
+        RtioClock::Ext0_Synth0_10to125 => { // 125 MHz output from 10 MHz CLKINx reference, 504 Hz BW
+            info!("using 10MHz reference to make 125MHz RTIO clock with PLL");
+            si5324::FrequencySettings {
+                n1_hs  : 10,
+                nc1_ls : 4,
+                n2_hs  : 10,
+                n2_ls  : 300,
+                n31    : 6,
+                n32    : 6,
+                bwsel  : 4,
+                crystal_ref: false
+            }
+        },
+        RtioClock::Ext0_Synth0_100to125 => { // 125MHz output, from 100MHz CLKINx reference, 586 Hz loop bandwidth
+            info!("using 10MHz reference to make 125MHz RTIO clock with PLL");
+            si5324::FrequencySettings {
+                n1_hs  : 10,
+                nc1_ls : 4,
+                n2_hs  : 10,
+                n2_ls  : 260,
+                n31    : 52,
+                n32    : 52,
+                bwsel  : 4,
+                crystal_ref: false
+            }
+        },
+        RtioClock::Ext0_Synth0_125to125 => { // 125MHz output, from 125MHz CLKINx reference, 606 Hz loop bandwidth
+            info!("using 10MHz reference to make 125MHz RTIO clock with PLL");
+            si5324::FrequencySettings {
+                n1_hs  : 5,
+                nc1_ls : 8,
+                n2_hs  : 7,
+                n2_ls  : 360,
+                n31    : 63,
+                n32    : 63,
+                bwsel  : 4,
+                crystal_ref: false
+            }
+        },
+        RtioClock::Int_150 => { // 150MHz output, from crystal
+            info!("using internal 150MHz RTIO clock");
+            si5324::FrequencySettings {
+                n1_hs  : 9,
+                nc1_ls : 4,
+                n2_hs  : 10,
+                n2_ls  : 33732,
+                n31    : 7139,
+                n32    : 7139,
+                bwsel  : 3,
+                crystal_ref: true
+            }
+        },
+        RtioClock::Int_100 => { // 100MHz output, from crystal. Also used as reference for Sayma HMC830.
+            info!("using internal 100MHz RTIO clock");
+            si5324::FrequencySettings {
+                n1_hs  : 9,
+                nc1_ls : 6,
+                n2_hs  : 10,
+                n2_ls  : 33732,
+                n31    : 7139,
+                n32    : 7139,
+                bwsel  : 3,
+                crystal_ref: true
+            }
+        },
         RtioClock::Int_125 => { // 125MHz output, from crystal, 7 Hz
             info!("using internal 125MHz RTIO clock");
             si5324::FrequencySettings {