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freq counter gw: refactor but still had bugs

This commit is contained in:
morgan 2024-03-28 17:05:33 +08:00
parent cd4169e571
commit fa5765383f
1 changed files with 23 additions and 15 deletions
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38
src/gateware/wrpll.py
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@ -7,7 +7,7 @@ from ddmtd import DDMTDSampler, DDMTD
from si549 import Si549 from si549 import Si549
class FrequencyCounter(Module, AutoCSR): class FrequencyCounter(Module, AutoCSR):
def __init__(self, domains, counter_width=24): def __init__(self, domains, counter_width=24, freq_divider=2):
self.update = CSR() self.update = CSR()
counter_reset = Signal() counter_reset = Signal()
@ -36,28 +36,33 @@ class FrequencyCounter(Module, AutoCSR):
) )
for domain in domains: for domain in domains:
divider = Signal(2)
divided_sys = Signal()
divided_sys_r = Signal()
rising = Signal()
name = "counter_" + domain name = "counter_" + domain
counter_csr = CSRStatus(counter_width, name=name) counter_csr = CSRStatus(counter_width, name=name)
setattr(self, name, counter_csr) setattr(self, name, counter_csr)
counter = Signal(counter_width)
counter = Signal(max=1 << freq_divider)
divided_counter = Signal(counter_width)
# # #
stb_ps = PulseSynchronizer(domain, "sys")
self.submodules += stb_ps
sync_domain = getattr(self.sync, domain) sync_domain = getattr(self.sync, domain)
sync_domain += divider.eq(divider + 1) sync_domain += [
self.specials += MultiReg(divider[-1], divided_sys) If(counter != 0,
self.sync += [ stb_ps.i.eq(0),
divided_sys_r.eq(divided_sys), counter.eq(counter - 1)
rising.eq(divided_sys & ~divided_sys_r) ).Else(
stb_ps.i.eq(1),
counter.eq((1 << freq_divider) - 1)
)
] ]
self.sync += [ self.sync += [
If(counter_reset, counter.eq(0)), If(counter_reset, divided_counter.eq(0)),
If(rising, counter.eq(counter + 1)), If(stb_ps.o, divided_counter.eq(divided_counter + 1)),
If(counter_stb, counter_csr.status.eq(counter)) If(counter_stb, counter_csr.status.eq(divided_counter))
] ]
class SkewTester(Module, AutoCSR): class SkewTester(Module, AutoCSR):
@ -85,6 +90,7 @@ class SkewTester(Module, AutoCSR):
class WRPLL(Module, AutoCSR): class WRPLL(Module, AutoCSR):
def __init__(self, platform, cd_ref, main_clk_se, COUNTER_BIT=32): def __init__(self, platform, cd_ref, main_clk_se, COUNTER_BIT=32):
self.refclk_reset = CSRStatus()
self.helper_reset = CSRStorage(reset=1) self.helper_reset = CSRStorage(reset=1)
self.ref_tag = CSRStatus(COUNTER_BIT) self.ref_tag = CSRStatus(COUNTER_BIT)
self.main_tag = CSRStatus(COUNTER_BIT) self.main_tag = CSRStatus(COUNTER_BIT)
@ -98,6 +104,8 @@ class WRPLL(Module, AutoCSR):
# # # # # #
self.sync += self.refclk_reset.status.eq(cd_ref.rst)
self.submodules.main_dcxo = Si549(platform.request("ddmtd_main_dcxo_i2c")) self.submodules.main_dcxo = Si549(platform.request("ddmtd_main_dcxo_i2c"))
self.submodules.helper_dcxo = Si549(platform.request("ddmtd_helper_dcxo_i2c")) self.submodules.helper_dcxo = Si549(platform.request("ddmtd_helper_dcxo_i2c"))