M-Labs/artiq-zynq
10
1
Fork 19
Code Issues 12 Pull Requests Releases Wiki Activity

panic on sysclk not switched

Browse Source
This commit is contained in:
mwojcik 2023-02-17 15:36:54 +08:00
parent 65678fb4c2
commit f7f956fc34
2 changed files with 14 additions and 11 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

13
src/runtime/src/rtio_clocking.rs
View File

@ -1,4 +1,4 @@
use log::{info, warn, error}; use log::{info, warn};
use libboard_zynq::timer::GlobalTimer; use libboard_zynq::timer::GlobalTimer;
use embedded_hal::blocking::delay::DelayMs; use embedded_hal::blocking::delay::DelayMs;
use libconfig::Config; use libconfig::Config;
@ -78,9 +78,8 @@ fn init_rtio(timer: &mut GlobalTimer) {
let clk = unsafe { pl::csr::sys_crg::current_clock_read() }; let clk = unsafe { pl::csr::sys_crg::current_clock_read() };
if clk == 1 { if clk == 1 {
info!("SYS CLK switched successfully"); info!("SYS CLK switched successfully");
} } else {
else { panic!("SYS CLK did not switch");
error!("SYS CLK did not switch");
} }
unsafe { unsafe {
pl::csr::rtio_core::reset_phy_write(1); pl::csr::rtio_core::reset_phy_write(1);
@ -92,7 +91,6 @@ fn init_rtio(timer: &mut GlobalTimer) {
#[cfg(has_drtio)] #[cfg(has_drtio)]
fn init_drtio(timer: &mut GlobalTimer) fn init_drtio(timer: &mut GlobalTimer)
{ {
timer.delay_ms(100); // wait for si output to really stabilize
unsafe { unsafe {
pl::csr::drtio_transceiver::stable_clkin_write(1); pl::csr::drtio_transceiver::stable_clkin_write(1);
} }
@ -101,9 +99,8 @@ fn init_drtio(timer: &mut GlobalTimer)
let clk = unsafe { pl::csr::sys_crg::current_clock_read() }; let clk = unsafe { pl::csr::sys_crg::current_clock_read() };
if clk == 1 { if clk == 1 {
info!("SYS CLK switched successfully"); info!("SYS CLK switched successfully");
} } else {
else { panic!("SYS CLK did not switch");
error!("SYS CLK did not switch");
} }
unsafe { unsafe {
pl::csr::rtio_core::reset_phy_write(1); pl::csr::rtio_core::reset_phy_write(1);

12
src/satman/src/main.rs
View File

@ -25,6 +25,8 @@ use libboard_artiq::si5324;
use libboard_artiq::{pl::csr, drtio_routing, drtioaux, logger, identifier_read}; use libboard_artiq::{pl::csr, drtio_routing, drtioaux, logger, identifier_read};
use libcortex_a9::{spin_lock_yield, interrupt_handler, regs::{MPIDR, SP}, notify_spin_lock, asm, l2c::enable_l2_cache}; use libcortex_a9::{spin_lock_yield, interrupt_handler, regs::{MPIDR, SP}, notify_spin_lock, asm, l2c::enable_l2_cache};
use libregister::{RegisterW, RegisterR}; use libregister::{RegisterW, RegisterR};
#[cfg(feature = "target_kasli_soc")]
use libboard_zynq::error_led::ErrorLED;
use embedded_hal::blocking::delay::DelayUs; use embedded_hal::blocking::delay::DelayUs;
use core::sync::atomic::{AtomicBool, Ordering}; use core::sync::atomic::{AtomicBool, Ordering};
@ -460,9 +462,8 @@ pub extern fn main_core0() -> i32 {
let clk = unsafe { csr::sys_crg::current_clock_read() }; let clk = unsafe { csr::sys_crg::current_clock_read() };
if clk == 1 { if clk == 1 {
info!("SYS CLK switched successfully"); info!("SYS CLK switched successfully");
} } else {
else { panic!("SYS CLK did not switch");
error!("SYS CLK did not switch");
} }
unsafe { unsafe {
@ -601,6 +602,11 @@ pub extern fn exception(_vect: u32, _regs: *const u32, pc: u32, ea: u32) {
#[panic_handler] #[panic_handler]
pub fn panic_fmt(info: &core::panic::PanicInfo) -> ! { pub fn panic_fmt(info: &core::panic::PanicInfo) -> ! {
let id = MPIDR.read().cpu_id() as usize; let id = MPIDR.read().cpu_id() as usize;
#[cfg(feature = "target_kasli_soc")]
{
let mut err_led = ErrorLED::error_led();
err_led.toggle(true);
}
print!("Core {} ", id); print!("Core {} ", id);
unsafe { unsafe {
if PANICKED[id] { if PANICKED[id] {