diff --git a/src/runtime/src/rtio_clocking.rs b/src/runtime/src/rtio_clocking.rs
index 1c39b66..5340e6d 100644
--- a/src/runtime/src/rtio_clocking.rs
+++ b/src/runtime/src/rtio_clocking.rs
@@ -1,4 +1,4 @@
-use log::{info, warn, error};
+use log::{info, warn};
 use libboard_zynq::timer::GlobalTimer;
 use embedded_hal::blocking::delay::DelayMs;
 use libconfig::Config;
@@ -78,9 +78,8 @@ fn init_rtio(timer: &mut GlobalTimer) {
     let clk = unsafe { pl::csr::sys_crg::current_clock_read() };
     if clk == 1 {
         info!("SYS CLK switched successfully");
-    }
-    else {
-        error!("SYS CLK did not switch");
+    } else {
+        panic!("SYS CLK did not switch");
     }
     unsafe {
         pl::csr::rtio_core::reset_phy_write(1);
@@ -92,7 +91,6 @@ fn init_rtio(timer: &mut GlobalTimer) {
 #[cfg(has_drtio)]
 fn init_drtio(timer: &mut GlobalTimer)
 {
-    timer.delay_ms(100); // wait for si output to really stabilize
     unsafe {
         pl::csr::drtio_transceiver::stable_clkin_write(1);
     }
@@ -101,9 +99,8 @@ fn init_drtio(timer: &mut GlobalTimer)
     let clk = unsafe { pl::csr::sys_crg::current_clock_read() };
     if clk == 1 {
         info!("SYS CLK switched successfully");
-    }
-    else {
-        error!("SYS CLK did not switch");
+    } else {
+        panic!("SYS CLK did not switch");
     }
     unsafe {
         pl::csr::rtio_core::reset_phy_write(1);
diff --git a/src/satman/src/main.rs b/src/satman/src/main.rs
index 95350ff..ae79d83 100644
--- a/src/satman/src/main.rs
+++ b/src/satman/src/main.rs
@@ -25,6 +25,8 @@ use libboard_artiq::si5324;
 use libboard_artiq::{pl::csr, drtio_routing, drtioaux, logger, identifier_read};
 use libcortex_a9::{spin_lock_yield, interrupt_handler, regs::{MPIDR, SP}, notify_spin_lock, asm, l2c::enable_l2_cache};
 use libregister::{RegisterW, RegisterR};
+#[cfg(feature = "target_kasli_soc")]
+use libboard_zynq::error_led::ErrorLED;
 
 use embedded_hal::blocking::delay::DelayUs;
 use core::sync::atomic::{AtomicBool, Ordering};
@@ -460,9 +462,8 @@ pub extern fn main_core0() -> i32 {
     let clk = unsafe { csr::sys_crg::current_clock_read() };
     if clk == 1 {
         info!("SYS CLK switched successfully");
-    }
-    else {
-        error!("SYS CLK did not switch");
+    } else {
+        panic!("SYS CLK did not switch");
     }
 
     unsafe {
@@ -601,6 +602,11 @@ pub extern fn exception(_vect: u32, _regs: *const u32, pc: u32, ea: u32) {
 #[panic_handler]
 pub fn panic_fmt(info: &core::panic::PanicInfo) -> ! {
     let id = MPIDR.read().cpu_id() as usize;
+    #[cfg(feature = "target_kasli_soc")]
+    {
+        let mut err_led = ErrorLED::error_led();
+        err_led.toggle(true);
+    }
     print!("Core {} ", id);
     unsafe {
         if PANICKED[id] {