M-Labs/artiq-zynq
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zc706: no syncrtio for master, fixes hangs (#188)

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mwojcik 2022-05-03 14:36:10 +08:00
parent 88ffd3b77b
commit efc432352e
1 changed files with 1 additions and 2 deletions
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3
src/gateware/zc706.py
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@ -311,10 +311,9 @@ class _MasterBase(SoCCore):
self.submodules.rtio_dma = dma.DMA(self.ps7.s_axi_hp0) self.submodules.rtio_dma = dma.DMA(self.ps7.s_axi_hp0)
self.csr_devices.append("rtio_dma") self.csr_devices.append("rtio_dma")
self.submodules.local_io = SyncRTIO(self.rtio_tsc, rtio_channels)
self.submodules.cri_con = rtio.CRIInterconnectShared( self.submodules.cri_con = rtio.CRIInterconnectShared(
[self.rtio.cri, self.rtio_dma.cri], [self.rtio.cri, self.rtio_dma.cri],
[self.local_io.cri] + self.drtio_cri, [self.rtio_core.cri] + self.drtio_cri,
mode="sync", enable_routing=True) mode="sync", enable_routing=True)
self.csr_devices.append("cri_con") self.csr_devices.append("cri_con")