From ecc8a0ccc0eb130be74a6f3cda7c41a0d5951976 Mon Sep 17 00:00:00 2001 From: mwojcik Date: Wed, 4 Aug 2021 16:44:08 +0200 Subject: [PATCH] kasli-soc: qpll is not part of this board, removed mentions --- src/gateware/kasli_soc.py | 14 -------------- 1 file changed, 14 deletions(-) diff --git a/src/gateware/kasli_soc.py b/src/gateware/kasli_soc.py index 6f62d82..0b0d514 100755 --- a/src/gateware/kasli_soc.py +++ b/src/gateware/kasli_soc.py @@ -213,11 +213,6 @@ class GenericMaster(SoCCore): data_pads=drtio_data_pads, sys_clk_freq=self.clk_freq) self.csr_devices.append("drtio_transceiver") - # todo figure out cdr lk clean - # self.sync += self.disable_cdr_clk_ibuf.eq( - # ~self.drtio_transceiver.stable_clkin.storage) - - # ====end drtio for now self.crg = self.ps7 # HACK for eem_7series to find the clock self.submodules.rtio_crg = RTIOCRG(self.platform) @@ -243,8 +238,6 @@ class GenericMaster(SoCCore): self.submodules.rtio_tsc = rtio.TSC("async", glbl_fine_ts_width=3) - # lifted from MasterBase - drtio_csr_group = [] drtioaux_csr_group = [] drtioaux_memory_group = [] @@ -278,8 +271,6 @@ class GenericMaster(SoCCore): self.add_csr_group("drtioaux", drtioaux_csr_group) self.add_memory_group("drtioaux_mem", drtioaux_memory_group) - # lift end - self.submodules.rtio_core = rtio.Core(self.rtio_tsc, self.rtio_channels) self.csr_devices.append("rtio_core") @@ -352,11 +343,6 @@ class GenericSatellite(SoCCore): data_pads=drtio_data_pads, sys_clk_freq=self.clk_freq) self.csr_devices.append("drtio_transceiver") - # same here - figure out the relations - # self.sync += disable_cdr_clk_ibuf.eq( - # ~self.drtio_transceiver.stable_clkin.storage) - - sfp_channels = self.drtio_transceiver.channels self.crg = self.ps7 # HACK for eem_7series to find the clock self.submodules.rtio_crg = RTIOCRG(self.platform)