diff --git a/src/gateware/kasli_soc.py b/src/gateware/kasli_soc.py
index 36dfad9..6060656 100755
--- a/src/gateware/kasli_soc.py
+++ b/src/gateware/kasli_soc.py
@@ -26,12 +26,12 @@ import analyzer
 import acpki
 import drtio_aux_controller
 
-class RTIOCRG(Module, AutoCSR):
+class SYSCRG(Module, AutoCSR):
     def __init__(self, platform):
         self.pll_reset = CSRStorage(reset=1)
         self.pll_locked = CSRStatus()
-        self.clock_domains.cd_rtio = ClockDomain()
-        self.clock_domains.cd_rtiox4 = ClockDomain(reset_less=True)
+        self.clock_domains.cd_sys = ClockDomain()
+        self.clock_domains.cd_sys4x = ClockDomain(reset_less=True)
 
         clk_synth = platform.request("cdr_clk_clean_fabric")
         clk_synth_se = Signal()
@@ -43,8 +43,8 @@ class RTIOCRG(Module, AutoCSR):
         ]
 
         pll_locked = Signal()
-        rtio_clk = Signal()
-        rtiox4_clk = Signal()
+        sys_clk = Signal()
+        sys4x_clk = Signal()
         fb_clk = Signal()
         self.specials += [
             Instance("PLLE2_ADV",
@@ -64,16 +64,16 @@ class RTIOCRG(Module, AutoCSR):
                      o_CLKFBOUT=fb_clk,
 
                      p_CLKOUT0_DIVIDE=3, p_CLKOUT0_PHASE=0.0,
-                     o_CLKOUT0=rtiox4_clk,
+                     o_CLKOUT0=sys4x_clk,
 
                      p_CLKOUT1_DIVIDE=12, p_CLKOUT1_PHASE=0.0,
-                     o_CLKOUT1=rtio_clk),
-            Instance("BUFG", i_I=rtio_clk, o_O=self.cd_rtio.clk),
-            Instance("BUFG", i_I=rtiox4_clk, o_O=self.cd_rtiox4.clk),
+                     o_CLKOUT1=sys_clk),
+            Instance("BUFG", i_I=sys_clk, o_O=self.cd_sys.clk),
+            Instance("BUFG", i_I=sys4x_clk, o_O=self.cd_sys4x.clk),
 
-            AsyncResetSynchronizer(self.cd_rtio, ~pll_locked),
-            MultiReg(pll_locked, self.pll_locked.status)
+            AsyncResetSynchronizer(self.cd_sys, ~pll_locked),
         ]
+        self.comb += self.pll_locked.status.eq(pll_locked)
 
         
 eem_iostandard_dict = {
@@ -121,7 +121,7 @@ class GenericStandalone(SoCCore):
         ident = description["variant"]
         if self.acpki:
             ident = "acpki_" + ident
-        SoCCore.__init__(self, platform=platform, csr_data_width=32, ident=ident)
+        SoCCore.__init__(self, platform=platform, csr_data_width=32, ident=ident, ps_cd_sys=False)
 
         platform.add_platform_command("create_clock -name clk_fpga_0 -period 8 [get_pins \"PS7/FCLKCLK[0]\"]")
         platform.add_platform_command("set_input_jitter clk_fpga_0 0.24")
@@ -132,12 +132,11 @@ class GenericStandalone(SoCCore):
         self.rustc_cfg["si5324_soft_reset"] = None
 
         self.crg = self.ps7 # HACK for eem_7series to find the clock
-        self.submodules.rtio_crg = RTIOCRG(self.platform)
-        self.csr_devices.append("rtio_crg")
-        self.platform.add_period_constraint(self.rtio_crg.cd_rtio.clk, 8.)
-        self.platform.add_false_path_constraints(
-            self.ps7.cd_sys.clk,
-            self.rtio_crg.cd_rtio.clk)
+        self.submodules.sys_crg = SYSCRG(self.platform)
+        self.csr_devices.append("sys_crg")
+        # another hack since ps7 itself does not have cd_sys anymore
+        self.crg.cd_sys = self.sys_crg.cd_sys
+        self.platform.add_period_constraint(self.sys_crg.cd_sys.clk, 8.)
 
         self.rtio_channels = []
         has_grabber = any(peripheral["type"] == "grabber" for peripheral in description["peripherals"])
@@ -189,7 +188,7 @@ class GenericStandalone(SoCCore):
             self.add_csr_group("grabber", self.grabber_csr_group)
             for grabber in self.grabber_csr_group:
                 self.platform.add_false_path_constraints(
-                    self.rtio_crg.cd_rtio.clk, getattr(self, grabber).deserializer.cd_cl.clk)
+                    self.sys_crg.cd_sys.clk, getattr(self, grabber).deserializer.cd_cl.clk)
 
 
 class GenericMaster(SoCCore):