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zc706 gateware: fix rust_cfg lacking has_si5324

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mwojcik 2021-08-02 15:06:29 +02:00
parent f70ce89ee6
commit e3e51b5ab1
1 changed files with 1 additions and 1 deletions
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2
src/gateware/zc706.py
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@ -82,7 +82,7 @@ class ZC706(SoCCore):
platform.add_platform_command("create_clock -name clk_fpga_0 -period 8 [get_pins \"PS7/FCLKCLK[0]\"]") platform.add_platform_command("create_clock -name clk_fpga_0 -period 8 [get_pins \"PS7/FCLKCLK[0]\"]")
platform.add_platform_command("set_input_jitter clk_fpga_0 0.24") platform.add_platform_command("set_input_jitter clk_fpga_0 0.24")
self.config["HAS_SI5324"] = None self.rustc_cfg["HAS_SI5324"] = None
self.submodules.si5324_rst_n = gpio.GPIOOut(platform.request("si5324").rst_n) self.submodules.si5324_rst_n = gpio.GPIOOut(platform.request("si5324").rst_n)
self.csr_devices.append("si5324_rst_n") self.csr_devices.append("si5324_rst_n")