M-Labs/artiq-zynq
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zc706: not actually ultrascale

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mwojcik 2021-11-29 12:48:45 +08:00
parent ada3f2e704
commit e045837b67
1 changed files with 1 additions and 1 deletions
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src/gateware/zc706.py
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@ -399,7 +399,7 @@ class _SatelliteBase(SoCCore):
self.submodules.siphaser = SiPhaser7Series(
si5324_clkin=platform.request("si5324_clkin"),
rx_synchronizer=self.rx_synchronizer,
ultrascale=True,
ultrascale=False,
rtio_clk_freq=self.drtio_transceiver.rtio_clk_freq)
platform.add_false_path_constraints(
self.ps7.cd_sys.clk, self.siphaser.mmcm_freerun_output)