prepared for rtioclkmultiplier/serdes in artiq
parent
0f8a7f3a4c
commit
df5436409d
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@ -15,7 +15,7 @@ from misoc.integration import cpu_interface
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from artiq.coredevice import jsondesc
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from artiq.gateware import rtio, eem_7series
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from artiq.gateware.rtio.phy import ttl_simple
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from artiq.gateware.rtio.xilinx_clocking import RTIOClockMultiplier
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from artiq.gateware.drtio.transceiver import gtx_7series
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from artiq.gateware.drtio.siphaser import SiPhaser7Series
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from artiq.gateware.drtio.rx_synchronizer import XilinxRXSynchronizer
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@ -75,36 +75,6 @@ class RTIOCRG(Module, AutoCSR):
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MultiReg(pll_locked, self.pll_locked.status)
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]
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class _RTIOClockMultiplier(Module, AutoCSR):
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def __init__(self, rtio_clk_freq):
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self.pll_reset = CSRStorage(reset=1)
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self.pll_locked = CSRStatus()
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self.clock_domains.cd_rtiox4 = ClockDomain(reset_less=True)
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# See "Global Clock Network Deskew Using Two BUFGs" in ug472.
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clkfbout = Signal()
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clkfbin = Signal()
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rtiox4_clk = Signal()
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pll_locked = Signal()
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self.specials += [
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Instance("MMCME2_BASE",
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p_CLKIN1_PERIOD=1e9/rtio_clk_freq,
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i_CLKIN1=ClockSignal("rtio"),
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i_RST=self.pll_reset.storage,
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o_LOCKED=pll_locked,
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p_CLKFBOUT_MULT_F=8.0, p_DIVCLK_DIVIDE=1,
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o_CLKFBOUT=clkfbout, i_CLKFBIN=clkfbin,
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p_CLKOUT0_DIVIDE_F=2.0, o_CLKOUT0=rtiox4_clk,
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),
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Instance("BUFG", i_I=clkfbout, o_O=clkfbin),
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Instance("BUFG", i_I=rtiox4_clk, o_O=self.cd_rtiox4.clk),
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MultiReg(pll_locked, self.pll_locked.status)
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]
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eem_iostandard_dict = {
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0: "LVDS_25",
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@ -238,7 +208,7 @@ class GenericMaster(SoCCore):
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self.csr_devices.append("drtio_transceiver")
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self.crg = self.ps7 # HACK for eem_7series to find the clock
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self.submodules.rtio_crg = _RTIOClockMultiplier(rtio_clk_freq)
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self.submodules.rtio_crg = RTIOClockMultiplier(rtio_clk_freq)
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self.csr_devices.append("rtio_crg")
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self.rtio_channels = []
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@ -350,7 +320,7 @@ class GenericSatellite(SoCCore):
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platform.add_platform_command("set_input_jitter clk_fpga_0 0.24")
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self.crg = self.ps7 # HACK for eem_7series to find the clock
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self.submodules.rtio_crg = _RTIOClockMultiplier(rtio_clk_freq)
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self.submodules.rtio_crg = RTIOClockMultiplier(rtio_clk_freq)
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self.csr_devices.append("rtio_crg")
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data_pads = [platform.request("sfp", i) for i in range(4)]
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@ -15,7 +15,7 @@ from misoc.cores import gpio
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from artiq.gateware import rtio, nist_clock, nist_qc2
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from artiq.gateware.rtio.phy import ttl_simple, ttl_serdes_7series, dds, spi2
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from artiq.gateware.rtio.xilinx_clocking import RTIOClockMultiplier, fix_serdes_timing_path
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from artiq.gateware.drtio.transceiver import gtx_7series
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from artiq.gateware.drtio.siphaser import SiPhaser7Series
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from artiq.gateware.drtio.rx_synchronizer import XilinxRXSynchronizer
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@ -26,6 +26,7 @@ import analyzer
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import acpki
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import drtio_aux_controller
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class RTIOCRG(Module, AutoCSR):
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def __init__(self, platform, rtio_internal_clk):
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self.clock_sel = CSRStorage()
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@ -70,48 +71,6 @@ class RTIOCRG(Module, AutoCSR):
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]
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class _RTIOClockMultiplier(Module, AutoCSR):
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def __init__(self, rtio_clk_freq):
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self.pll_reset = CSRStorage(reset=1)
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self.pll_locked = CSRStatus()
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self.clock_domains.cd_rtiox4 = ClockDomain(reset_less=True)
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# See "Global Clock Network Deskew Using Two BUFGs" in ug472.
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clkfbout = Signal()
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clkfbin = Signal()
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rtiox4_clk = Signal()
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pll_locked = Signal()
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self.specials += [
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Instance("MMCME2_BASE",
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p_CLKIN1_PERIOD=1e9/rtio_clk_freq,
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i_CLKIN1=ClockSignal("rtio"),
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i_RST=self.pll_reset.storage,
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o_LOCKED=pll_locked,
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p_CLKFBOUT_MULT_F=8.0, p_DIVCLK_DIVIDE=1,
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o_CLKFBOUT=clkfbout, i_CLKFBIN=clkfbin,
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p_CLKOUT0_DIVIDE_F=2.0, o_CLKOUT0=rtiox4_clk,
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),
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Instance("BUFG", i_I=clkfbout, o_O=clkfbin),
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Instance("BUFG", i_I=rtiox4_clk, o_O=self.cd_rtiox4.clk),
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MultiReg(pll_locked, self.pll_locked.status)
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]
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def fix_serdes_timing_path(platform):
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# ignore timing of path from OSERDESE2 through the pad to ISERDESE2
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platform.add_platform_command(
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"set_false_path -quiet "
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"-through [get_pins -filter {{REF_PIN_NAME == OQ || REF_PIN_NAME == TQ}} "
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"-of [get_cells -filter {{REF_NAME == OSERDESE2}}]] "
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"-to [get_pins -filter {{REF_PIN_NAME == D}} "
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"-of [get_cells -filter {{REF_NAME == ISERDESE2}}]]"
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)
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# The NIST backplanes require setting VADJ to 3.3V by reprogramming the power supply.
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# This also changes the I/O standard for some on-board LEDs.
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leds_fmc33 = [
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@ -288,7 +247,7 @@ class _MasterBase(SoCCore):
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platform.add_false_path_constraints(
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self.ps7.cd_sys.clk, gtx0.txoutclk, gtx.rxoutclk)
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self.submodules.rtio_crg = _RTIOClockMultiplier(self.sys_clk_freq)
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self.submodules.rtio_crg = RTIOClockMultiplier(self.sys_clk_freq)
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self.csr_devices.append("rtio_crg")
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fix_serdes_timing_path(self.platform)
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@ -437,7 +396,7 @@ class _SatelliteBase(SoCCore):
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platform.add_false_path_constraints(
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self.ps7.cd_sys.clk, gtx.rxoutclk)
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self.submodules.rtio_crg = _RTIOClockMultiplier(self.sys_clk_freq)
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self.submodules.rtio_crg = RTIOClockMultiplier(self.sys_clk_freq)
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self.csr_devices.append("rtio_crg")
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fix_serdes_timing_path(self.platform)
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