prepared for rtioclkmultiplier/serdes in artiq
This commit is contained in:
parent
0f8a7f3a4c
commit
df5436409d
|
|
@ -15,7 +15,7 @@ from misoc.integration import cpu_interface
|
|||
from artiq.coredevice import jsondesc
|
||||
from artiq.gateware import rtio, eem_7series
|
||||
from artiq.gateware.rtio.phy import ttl_simple
|
||||
|
||||
from artiq.gateware.rtio.xilinx_clocking import RTIOClockMultiplier
|
||||
from artiq.gateware.drtio.transceiver import gtx_7series
|
||||
from artiq.gateware.drtio.siphaser import SiPhaser7Series
|
||||
from artiq.gateware.drtio.rx_synchronizer import XilinxRXSynchronizer
|
||||
|
|
@ -75,36 +75,6 @@ class RTIOCRG(Module, AutoCSR):
|
|||
MultiReg(pll_locked, self.pll_locked.status)
|
||||
]
|
||||
|
||||
|
||||
class _RTIOClockMultiplier(Module, AutoCSR):
|
||||
def __init__(self, rtio_clk_freq):
|
||||
self.pll_reset = CSRStorage(reset=1)
|
||||
self.pll_locked = CSRStatus()
|
||||
self.clock_domains.cd_rtiox4 = ClockDomain(reset_less=True)
|
||||
|
||||
# See "Global Clock Network Deskew Using Two BUFGs" in ug472.
|
||||
clkfbout = Signal()
|
||||
clkfbin = Signal()
|
||||
rtiox4_clk = Signal()
|
||||
pll_locked = Signal()
|
||||
self.specials += [
|
||||
Instance("MMCME2_BASE",
|
||||
p_CLKIN1_PERIOD=1e9/rtio_clk_freq,
|
||||
i_CLKIN1=ClockSignal("rtio"),
|
||||
i_RST=self.pll_reset.storage,
|
||||
o_LOCKED=pll_locked,
|
||||
|
||||
p_CLKFBOUT_MULT_F=8.0, p_DIVCLK_DIVIDE=1,
|
||||
|
||||
o_CLKFBOUT=clkfbout, i_CLKFBIN=clkfbin,
|
||||
|
||||
p_CLKOUT0_DIVIDE_F=2.0, o_CLKOUT0=rtiox4_clk,
|
||||
),
|
||||
Instance("BUFG", i_I=clkfbout, o_O=clkfbin),
|
||||
Instance("BUFG", i_I=rtiox4_clk, o_O=self.cd_rtiox4.clk),
|
||||
|
||||
MultiReg(pll_locked, self.pll_locked.status)
|
||||
]
|
||||
|
||||
eem_iostandard_dict = {
|
||||
0: "LVDS_25",
|
||||
|
|
@ -238,7 +208,7 @@ class GenericMaster(SoCCore):
|
|||
self.csr_devices.append("drtio_transceiver")
|
||||
|
||||
self.crg = self.ps7 # HACK for eem_7series to find the clock
|
||||
self.submodules.rtio_crg = _RTIOClockMultiplier(rtio_clk_freq)
|
||||
self.submodules.rtio_crg = RTIOClockMultiplier(rtio_clk_freq)
|
||||
self.csr_devices.append("rtio_crg")
|
||||
|
||||
self.rtio_channels = []
|
||||
|
|
@ -350,7 +320,7 @@ class GenericSatellite(SoCCore):
|
|||
platform.add_platform_command("set_input_jitter clk_fpga_0 0.24")
|
||||
|
||||
self.crg = self.ps7 # HACK for eem_7series to find the clock
|
||||
self.submodules.rtio_crg = _RTIOClockMultiplier(rtio_clk_freq)
|
||||
self.submodules.rtio_crg = RTIOClockMultiplier(rtio_clk_freq)
|
||||
self.csr_devices.append("rtio_crg")
|
||||
|
||||
data_pads = [platform.request("sfp", i) for i in range(4)]
|
||||
|
|
|
|||
|
|
@ -15,7 +15,7 @@ from misoc.cores import gpio
|
|||
|
||||
from artiq.gateware import rtio, nist_clock, nist_qc2
|
||||
from artiq.gateware.rtio.phy import ttl_simple, ttl_serdes_7series, dds, spi2
|
||||
|
||||
from artiq.gateware.rtio.xilinx_clocking import RTIOClockMultiplier, fix_serdes_timing_path
|
||||
from artiq.gateware.drtio.transceiver import gtx_7series
|
||||
from artiq.gateware.drtio.siphaser import SiPhaser7Series
|
||||
from artiq.gateware.drtio.rx_synchronizer import XilinxRXSynchronizer
|
||||
|
|
@ -26,6 +26,7 @@ import analyzer
|
|||
import acpki
|
||||
import drtio_aux_controller
|
||||
|
||||
|
||||
class RTIOCRG(Module, AutoCSR):
|
||||
def __init__(self, platform, rtio_internal_clk):
|
||||
self.clock_sel = CSRStorage()
|
||||
|
|
@ -70,48 +71,6 @@ class RTIOCRG(Module, AutoCSR):
|
|||
]
|
||||
|
||||
|
||||
class _RTIOClockMultiplier(Module, AutoCSR):
|
||||
def __init__(self, rtio_clk_freq):
|
||||
self.pll_reset = CSRStorage(reset=1)
|
||||
self.pll_locked = CSRStatus()
|
||||
self.clock_domains.cd_rtiox4 = ClockDomain(reset_less=True)
|
||||
|
||||
# See "Global Clock Network Deskew Using Two BUFGs" in ug472.
|
||||
clkfbout = Signal()
|
||||
clkfbin = Signal()
|
||||
rtiox4_clk = Signal()
|
||||
pll_locked = Signal()
|
||||
self.specials += [
|
||||
Instance("MMCME2_BASE",
|
||||
p_CLKIN1_PERIOD=1e9/rtio_clk_freq,
|
||||
i_CLKIN1=ClockSignal("rtio"),
|
||||
i_RST=self.pll_reset.storage,
|
||||
o_LOCKED=pll_locked,
|
||||
|
||||
p_CLKFBOUT_MULT_F=8.0, p_DIVCLK_DIVIDE=1,
|
||||
|
||||
o_CLKFBOUT=clkfbout, i_CLKFBIN=clkfbin,
|
||||
|
||||
p_CLKOUT0_DIVIDE_F=2.0, o_CLKOUT0=rtiox4_clk,
|
||||
),
|
||||
Instance("BUFG", i_I=clkfbout, o_O=clkfbin),
|
||||
Instance("BUFG", i_I=rtiox4_clk, o_O=self.cd_rtiox4.clk),
|
||||
|
||||
MultiReg(pll_locked, self.pll_locked.status)
|
||||
]
|
||||
|
||||
|
||||
def fix_serdes_timing_path(platform):
|
||||
# ignore timing of path from OSERDESE2 through the pad to ISERDESE2
|
||||
platform.add_platform_command(
|
||||
"set_false_path -quiet "
|
||||
"-through [get_pins -filter {{REF_PIN_NAME == OQ || REF_PIN_NAME == TQ}} "
|
||||
"-of [get_cells -filter {{REF_NAME == OSERDESE2}}]] "
|
||||
"-to [get_pins -filter {{REF_PIN_NAME == D}} "
|
||||
"-of [get_cells -filter {{REF_NAME == ISERDESE2}}]]"
|
||||
)
|
||||
|
||||
|
||||
# The NIST backplanes require setting VADJ to 3.3V by reprogramming the power supply.
|
||||
# This also changes the I/O standard for some on-board LEDs.
|
||||
leds_fmc33 = [
|
||||
|
|
@ -288,7 +247,7 @@ class _MasterBase(SoCCore):
|
|||
platform.add_false_path_constraints(
|
||||
self.ps7.cd_sys.clk, gtx0.txoutclk, gtx.rxoutclk)
|
||||
|
||||
self.submodules.rtio_crg = _RTIOClockMultiplier(self.sys_clk_freq)
|
||||
self.submodules.rtio_crg = RTIOClockMultiplier(self.sys_clk_freq)
|
||||
self.csr_devices.append("rtio_crg")
|
||||
fix_serdes_timing_path(self.platform)
|
||||
|
||||
|
|
@ -437,7 +396,7 @@ class _SatelliteBase(SoCCore):
|
|||
platform.add_false_path_constraints(
|
||||
self.ps7.cd_sys.clk, gtx.rxoutclk)
|
||||
|
||||
self.submodules.rtio_crg = _RTIOClockMultiplier(self.sys_clk_freq)
|
||||
self.submodules.rtio_crg = RTIOClockMultiplier(self.sys_clk_freq)
|
||||
self.csr_devices.append("rtio_crg")
|
||||
fix_serdes_timing_path(self.platform)
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue