M-Labs/artiq-zynq
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kasli_soc: fix si5324 pins routed to GTX

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This commit is contained in:
mwojcik 2022-04-25 12:33:21 +08:00
parent f9a8c76654
commit def4d989cd
1 changed files with 2 additions and 2 deletions
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4
src/gateware/kasli_soc.py
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@ -217,7 +217,7 @@ class GenericMaster(SoCCore):
data_pads = [platform.request("sfp", i) for i in range(4)] data_pads = [platform.request("sfp", i) for i in range(4)]
self.submodules.drtio_transceiver = gtx_7series.GTX( self.submodules.drtio_transceiver = gtx_7series.GTX(
clock_pads=platform.request("clk125_gtp"), clock_pads=platform.request("clk_gtp"),
pads=data_pads, pads=data_pads,
sys_clk_freq=sys_clk_freq) sys_clk_freq=sys_clk_freq)
self.csr_devices.append("drtio_transceiver") self.csr_devices.append("drtio_transceiver")
@ -345,7 +345,7 @@ class GenericSatellite(SoCCore):
data_pads = [platform.request("sfp", i) for i in range(4)] data_pads = [platform.request("sfp", i) for i in range(4)]
self.submodules.drtio_transceiver = gtx_7series.GTX( self.submodules.drtio_transceiver = gtx_7series.GTX(
clock_pads=platform.request("clk125_gtp"), clock_pads=platform.request("clk_gtp"),
pads=data_pads, pads=data_pads,
sys_clk_freq=sys_clk_freq) sys_clk_freq=sys_clk_freq)
self.csr_devices.append("drtio_transceiver") self.csr_devices.append("drtio_transceiver")