diff --git a/src/gateware/zc706.py b/src/gateware/zc706.py index 095e47c..8a808f2 100755 --- a/src/gateware/zc706.py +++ b/src/gateware/zc706.py @@ -28,49 +28,6 @@ import drtio_aux_controller import zynq_clocking -class SYSCRG(Module, AutoCSR): - def __init__(self, platform, ps7, main_clk): - self.pll_locked = CSRStatus() - self.pll_clksel = CSRStorage() - self.pll_reset = CSRStorage() - self.clock_domains.cd_sys = ClockDomain() - self.clock_domains.cd_sys4x = ClockDomain(reset_less=True) - - pll_locked = Signal() - sys_clk = Signal() - sys4x_clk = Signal() - fb_clk = Signal() - fclk_buf = Signal() - self.specials += [ - Instance("BUFG", i_I=ps7.fclk.clk[0], o_O=fclk_buf), - Instance("PLLE2_ADV", - p_STARTUP_WAIT="FALSE", o_LOCKED=pll_locked, - p_BANDWIDTH="HIGH", - p_REF_JITTER1=0.001, - p_CLKIN1_PERIOD=8.0, i_CLKIN1=main_clk, - p_CLKIN2_PERIOD=8.0, i_CLKIN2=fclk_buf, - i_CLKINSEL=self.pll_clksel.storage, - - # VCO @ 1.5GHz when using 125MHz input - p_CLKFBOUT_MULT=12, p_DIVCLK_DIVIDE=1, - i_CLKFBIN=fb_clk, - i_RST=self.pll_reset.storage, - - o_CLKFBOUT=fb_clk, - - p_CLKOUT0_DIVIDE=12, p_CLKOUT0_PHASE=0.0, - o_CLKOUT0=sys_clk, - p_CLKOUT1_DIVIDE=3, p_CLKOUT1_PHASE=0.0, - o_CLKOUT1=sys4x_clk), - Instance("BUFG", i_I=sys_clk, o_O=self.cd_sys.clk), - Instance("BUFG", i_I=sys4x_clk, o_O=self.cd_sys4x.clk), - AsyncResetSynchronizer(self.cd_sys, ~pll_locked) - ] - self.comb += self.pll_locked.status.eq(pll_locked) - platform.add_period_constraint(fclk_buf, 8.) - platform.add_false_path_constraints(self.cd_sys.clk, fclk_buf, main_clk) - - class SMAClkinForward(Module): def __init__(self, platform): sma_clkin = platform.request("user_sma_clock") @@ -173,9 +130,8 @@ class ZC706(SoCCore): self.rustc_cfg["si5324_as_synthesizer"] = None self.rustc_cfg["si5324_soft_reset"] = None - self.submodules.sys_crg = SYSCRG(self.platform, self.ps7, cdr_clk_buf) + self.submodules.sys_crg = zynq_clocking.SYSCRG(self.platform, self.ps7, cdr_clk_buf) self.csr_devices.append("sys_crg") - self.platform.add_period_constraint(self.sys_crg.cd_sys.clk, 8.) def add_rtio(self, rtio_channels): self.submodules.rtio_tsc = rtio.TSC(glbl_fine_ts_width=3) @@ -215,20 +171,17 @@ class _MasterBase(SoCCore): self.acpki = acpki self.rustc_cfg = dict() + clk_freq = 100e6 if drtio100mhz else 125e6 + platform = zc706.Platform() prepare_zc706_platform(platform) ident = self.__class__.__name__ if self.acpki: ident = "acpki_" + ident - SoCCore.__init__(self, platform=platform, csr_data_width=32, ident=ident) + SoCCore.__init__(self, platform=platform, csr_data_width=32, ident=ident, ps_cd_sys=False) platform.add_extension(si5324_fmc33) - self.sys_clk_freq = 125e6 - rtio_clk_freq = 100e6 if drtio100mhz else self.sys_clk_freq - - platform = self.platform - self.comb += platform.request("sfp_tx_disable_n").eq(1) data_pads = [ platform.request("sfp"), @@ -241,11 +194,20 @@ class _MasterBase(SoCCore): self.submodules.drtio_transceiver = gtx_7series.GTX( clock_pads=platform.request("si5324_clkout"), pads=data_pads, - sys_clk_freq=self.sys_clk_freq, - rtio_clk_freq=rtio_clk_freq) + clk_freq=clk_freq) self.csr_devices.append("drtio_transceiver") self.submodules.rtio_tsc = rtio.TSC(glbl_fine_ts_width=3) + txout_buf = Signal() + self.specials += Instance( + "BUFG", + i_I=self.drtio_transceiver.gtxs[0].txoutclk, + o_O=txout_buf) + self.submodules.sys_crg = zynq_clocking.SYSCRG( + self.platform, + self.ps7, + txout_buf) + self.csr_devices.append("sys_crg") drtio_csr_group = [] drtioaux_csr_group = [] @@ -288,25 +250,18 @@ class _MasterBase(SoCCore): self.rustc_cfg["has_si5324"] = None self.rustc_cfg["si5324_as_synthesizer"] = None - rtio_clk_period = 1e9/self.drtio_transceiver.rtio_clk_freq # Constrain TX & RX timing for the first transceiver channel # (First channel acts as master for phase alignment for all channels' TX) gtx0 = self.drtio_transceiver.gtxs[0] - platform.add_period_constraint(gtx0.txoutclk, rtio_clk_period) - platform.add_period_constraint(gtx0.rxoutclk, rtio_clk_period) platform.add_false_path_constraints( - self.ps7.cd_sys.clk, gtx0.txoutclk, gtx0.rxoutclk) # Constrain RX timing for the each transceiver channel # (Each channel performs single-lane phase alignment for RX) for gtx in self.drtio_transceiver.gtxs[1:]: - platform.add_period_constraint(gtx.rxoutclk, rtio_clk_period) platform.add_false_path_constraints( - self.ps7.cd_sys.clk, gtx0.txoutclk, gtx.rxoutclk) + gtx0.txoutclk, gtx.rxoutclk) - self.submodules.rtio_crg = RTIOClockMultiplier(self.sys_clk_freq) - self.csr_devices.append("rtio_crg") - fix_serdes_timing_path(self.platform) + fix_serdes_timing_path(platform) def add_rtio(self, rtio_channels): self.submodules.rtio_tsc = rtio.TSC(glbl_fine_ts_width=3) @@ -331,7 +286,7 @@ class _MasterBase(SoCCore): self.submodules.cri_con = rtio.CRIInterconnectShared( [self.rtio.cri, self.rtio_dma.cri], [self.rtio_core.cri] + self.drtio_cri, - mode="sync", enable_routing=True) + enable_routing=True) self.csr_devices.append("cri_con") self.submodules.rtio_moninj = rtio.MonInj(rtio_channels) @@ -350,19 +305,17 @@ class _SatelliteBase(SoCCore): self.acpki = acpki self.rustc_cfg = dict() + clk_freq = 100e6 if drtio100mhz else 125e6 + platform = zc706.Platform() prepare_zc706_platform(platform) ident = self.__class__.__name__ if self.acpki: ident = "acpki_" + ident - SoCCore.__init__(self, platform=platform, csr_data_width=32, ident=ident) + SoCCore.__init__(self, platform=platform, csr_data_width=32, ident=ident, ps_cd_sys=False) platform.add_extension(si5324_fmc33) - self.sys_clk_freq = 125e6 - rtio_clk_freq = 100e6 if drtio100mhz else self.sys_clk_freq - platform = self.platform - # SFP self.comb += platform.request("sfp_tx_disable_n").eq(0) data_pads = [ @@ -376,10 +329,21 @@ class _SatelliteBase(SoCCore): self.submodules.drtio_transceiver = gtx_7series.GTX( clock_pads=platform.request("si5324_clkout"), pads=data_pads, - sys_clk_freq=self.sys_clk_freq, - rtio_clk_freq=rtio_clk_freq) + clk_freq=clk_freq) self.csr_devices.append("drtio_transceiver") + txout_buf = Signal() + txout_buf.attr.add("keep") + self.specials += Instance( + "BUFG", + i_I=self.drtio_transceiver.gtxs[0].txoutclk, + o_O=txout_buf) + self.submodules.sys_crg = zynq_clocking.SYSCRG( + self.platform, + self.ps7, + txout_buf) + self.csr_devices.append("sys_crg") + drtioaux_csr_group = [] drtioaux_memory_group = [] drtiorep_csr_group = [] @@ -437,7 +401,7 @@ class _SatelliteBase(SoCCore): ultrascale=False, rtio_clk_freq=self.drtio_transceiver.rtio_clk_freq) platform.add_false_path_constraints( - self.ps7.cd_sys.clk, self.siphaser.mmcm_freerun_output) + self.sys_crg.cd_sys.clk, self.siphaser.mmcm_freerun_output) self.csr_devices.append("siphaser") self.submodules.si5324_rst_n = gpio.GPIOOut(platform.request("si5324_33").rst_n) self.csr_devices.append("si5324_rst_n") @@ -448,22 +412,15 @@ class _SatelliteBase(SoCCore): # Constrain TX & RX timing for the first transceiver channel # (First channel acts as master for phase alignment for all channels' TX) gtx0 = self.drtio_transceiver.gtxs[0] - platform.add_period_constraint(gtx0.txoutclk, rtio_clk_period) - platform.add_period_constraint(gtx0.rxoutclk, rtio_clk_period) platform.add_false_path_constraints( - self.ps7.cd_sys.clk, gtx0.txoutclk, gtx0.rxoutclk) # Constrain RX timing for the each transceiver channel # (Each channel performs single-lane phase alignment for RX) for gtx in self.drtio_transceiver.gtxs[1:]: - platform.add_period_constraint(gtx.rxoutclk, rtio_clk_period) platform.add_false_path_constraints( - self.ps7.cd_sys.clk, gtx.rxoutclk) + self.sys_crg.cd_sys.clk, gtx.rxoutclk) - self.submodules.rtio_crg = RTIOClockMultiplier(self.sys_clk_freq) - self.csr_devices.append("rtio_crg") - self.rustc_cfg["has_rtio_crg"] = None - fix_serdes_timing_path(self.platform) + fix_serdes_timing_path(platform) def add_rtio(self, rtio_channels): self.submodules.rtio_moninj = rtio.MonInj(rtio_channels) @@ -485,7 +442,7 @@ class _SatelliteBase(SoCCore): self.submodules.cri_con = rtio.CRIInterconnectShared( [self.drtiosat.cri], [self.local_io.cri] + self.drtio_cri, - mode="sync", enable_routing=True) + enable_routing=True) self.csr_devices.append("cri_con") self.submodules.routing_table = rtio.RoutingTableAccess(self.cri_con)