M-Labs/artiq-zynq
10
1
Fork 19
Code Issues 12 Pull Requests Releases Wiki Activity

aux_controller: fix class parent

Browse Source
This commit is contained in:
mwojcik 2021-10-04 08:53:38 +02:00
parent b9da4c27fe
commit db1c9d336e
1 changed files with 1 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
src/gateware/aux_controller.py
View File

@ -72,7 +72,7 @@ class DRTIOAuxControllerAxi(_DRTIOAuxControllerBase):
@FullMemoryWE() @FullMemoryWE()
class DRTIOAuxControllerBare(Module): class DRTIOAuxControllerBare(_DRTIOAuxControllerBase):
# Barebones version of the AuxController. No SRAM, no decoders. # Barebones version of the AuxController. No SRAM, no decoders.
# add memories manually from tx and rx in target code. # add memories manually from tx and rx in target code.
def get_tx_port(self): def get_tx_port(self):