diff --git a/src/gateware/kasli_soc.py b/src/gateware/kasli_soc.py
index d6325db..7140782 100755
--- a/src/gateware/kasli_soc.py
+++ b/src/gateware/kasli_soc.py
@@ -272,9 +272,7 @@ class GenericMaster(SoCCore):
             self.csr_devices.append(coreaux_name)
 
             memory_address = self.mem_map["drtioaux"] + 0x800*i
-            self.add_wb_slave(memory_address, 0x800,
-                              coreaux.bus)
-            self.add_memory_region(memory_name, memory_address | self.shadow_base, 0x800)
+            self.register_mem(memory_name, memory_address, 0x800, coreaux.bus)
         self.config["HAS_DRTIO"] = None
         self.config["HAS_DRTIO_ROUTING"] = None
         self.add_csr_group("drtio", drtio_csr_group)
@@ -422,9 +420,7 @@ class GenericSatellite(SoCCore):
             self.csr_devices.append(coreaux_name)
 
             memory_address = self.mem_map["drtioaux"] + 0x800*i
-            self.add_wb_slave(memory_address, 0x800,
-                              coreaux.bus)
-            self.add_memory_region(memory_name, memory_address | self.shadow_base, 0x800)
+            self.register_mem(memory_name, memory_address, 0x800, coreaux.bus)
         self.config["HAS_DRTIO"] = None
         self.config["HAS_DRTIO_ROUTING"] = None
         self.add_csr_group("drtioaux", drtioaux_csr_group)
diff --git a/src/gateware/zc706.py b/src/gateware/zc706.py
index 28466df..01b28e3 100755
--- a/src/gateware/zc706.py
+++ b/src/gateware/zc706.py
@@ -270,7 +270,7 @@ class Master(ZC706):
         ZC706.__init__(self, **kwargs)
 
         sys_clk_freq = 125e6
-        
+
         platform = self.platform
 
         self.comb += platform.request("sfp_tx_disable_n").eq(1)
@@ -316,9 +316,7 @@ class Master(ZC706):
             self.csr_devices.append(coreaux_name)
 
             memory_address = self.mem_map["drtioaux"] + 0x800*i
-            self.add_wb_slave(memory_address, 0x800,
-                              coreaux.bus)
-            self.add_memory_region(memory_name, memory_address | self.shadow_base, 0x800)
+            self.register_mem(memory_name, memory_address, 0x800, coreaux.bus)
         self.config["HAS_DRTIO"] = None
         self.config["HAS_DRTIO_ROUTING"] = None
         self.add_csr_group("drtio", drtio_csr_group)
@@ -428,9 +426,7 @@ class Satellite(ZC706):
             self.csr_devices.append(coreaux_name)
 
             memory_address = self.mem_map["drtioaux"] + 0x800*i
-            self.add_wb_slave(memory_address, 0x800,
-                              coreaux.bus)
-            self.add_memory_region(memory_name, memory_address | self.shadow_base, 0x800)
+            self.register_mem(memory_name, memory_address, 0x800, coreaux.bus)
         self.config["HAS_DRTIO"] = None
         self.config["HAS_DRTIO_ROUTING"] = None
         self.add_csr_group("drtioaux", drtioaux_csr_group)