M-Labs/artiq-zynq
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changed auxctrl tx/rx memory to axi2csr_sram

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mwojcik 2021-09-10 15:25:05 +02:00
parent 9c14694fc4
commit d3152f3d24
3 changed files with 31 additions and 10 deletions
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13
src/gateware/aux_controller.py
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@ -17,7 +17,6 @@ class DRTIOAuxControllerAxi(Module):
self.submodules.transmitter = Transmitter(link_layer, len(self.bus.w.data)) self.submodules.transmitter = Transmitter(link_layer, len(self.bus.w.data))
self.submodules.receiver = Receiver(link_layer, len(self.bus.w.data)) self.submodules.receiver = Receiver(link_layer, len(self.bus.w.data))
# probably will need to make axi.SRAM based on wb code
tx_sdram_if = SRAM(self.transmitter.mem, read_only=False) tx_sdram_if = SRAM(self.transmitter.mem, read_only=False)
rx_sdram_if = SRAM(self.receiver.mem, read_only=True) rx_sdram_if = SRAM(self.receiver.mem, read_only=True)
wsb = log2_int(len(self.bus.w.data)//8) wsb = log2_int(len(self.bus.w.data)//8)
@ -33,3 +32,15 @@ class DRTIOAuxControllerAxi(Module):
def get_csrs(self): def get_csrs(self):
return self.transmitter.get_csrs() + self.receiver.get_csrs() return self.transmitter.get_csrs() + self.receiver.get_csrs()
@FullMemoryWE()
class DRTIOAuxControllerBare(Module):
# Barebones version of the AuxController. No SRAM, no decoders.
# add memories manually from tx and rx in target code.
def __init__(self, link_layer):
self.bus = axi.Interface()
self.submodules.transmitter = Transmitter(link_layer, len(self.bus.w.data))
self.submodules.receiver = Receiver(link_layer, len(self.bus.w.data))
def get_csrs(self):
return self.transmitter.get_csrs() + self.receiver.get_csrs()

18
src/gateware/kasli_soc.py
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@ -288,12 +288,14 @@ class GenericMaster(SoCCore):
self.drtio_cri.append(core.cri) self.drtio_cri.append(core.cri)
self.csr_devices.append(core_name) self.csr_devices.append(core_name)
coreaux = cdr(aux_controller.DRTIOAuxControllerAxi(core.link_layer)) coreaux = cdr(aux_controller.DRTIOAuxControllerBare(core.link_layer))
setattr(self.submodules, coreaux_name, coreaux) setattr(self.submodules, coreaux_name, coreaux)
self.csr_devices.append(coreaux_name) self.csr_devices.append(coreaux_name)
memory_address = self.mem_map["drtioaux"] + 0x800*i memory_address, size = self.axi2csr.add_memory(coreaux.transmitter.mem, read_only=False)
self.register_mem(memory_name, memory_address, 0x800, coreaux.bus) # rcv in upper half of the memory, thus added second
self.axi2csr.add_memory(coreaux.receiver.mem, read_only=False)
self.add_memory_region(memory_name, self.mem_map["csr"] + memory_address, size * 2)
self.rustc_cfg["has_drtio"] = None self.rustc_cfg["has_drtio"] = None
self.rustc_cfg["has_drtio_routing"] = None self.rustc_cfg["has_drtio_routing"] = None
self.add_csr_group("drtio", drtio_csr_group) self.add_csr_group("drtio", drtio_csr_group)
@ -427,12 +429,16 @@ class GenericSatellite(SoCCore):
self.drtio_cri.append(core.cri) self.drtio_cri.append(core.cri)
self.csr_devices.append(corerep_name) self.csr_devices.append(corerep_name)
coreaux = cdr(aux_controller.DRTIOAuxControllerAxi(core.link_layer)) coreaux = cdr(aux_controller.DRTIOAuxControllerBare(core.link_layer))
setattr(self.submodules, coreaux_name, coreaux) setattr(self.submodules, coreaux_name, coreaux)
self.csr_devices.append(coreaux_name) self.csr_devices.append(coreaux_name)
memory_address = self.mem_map["drtioaux"] + 0x800*i memory_address, size = self.axi2csr.add_memory(coreaux.transmitter.mem, read_only=False)
self.register_mem(memory_name, memory_address, 0x800, coreaux.bus) # rcv in upper half of the memory, thus added second
self.axi2csr.add_memory(coreaux.receiver.mem, read_only=False)
# and registered in PS interface
# manually, because software refers to rx/tx by halves of entire memory block, not names
self.add_memory_region(memory_name, self.mem_map["csr"] + memory_address, size * 2)
self.config["has_drtio"] = None self.config["has_drtio"] = None
self.config["has_drtio_routing"] = None self.config["has_drtio_routing"] = None
self.add_csr_group("drtioaux", drtioaux_csr_group) self.add_csr_group("drtioaux", drtioaux_csr_group)

10
src/gateware/zc706.py
View File

@ -330,12 +330,16 @@ class _SatelliteBase(SoCCore):
# Repeaters - there would be for i != 0 - however zc706 only has one SFP # Repeaters - there would be for i != 0 - however zc706 only has one SFP
# and no other means to connect to # and no other means to connect to
coreaux = cdr(aux_controller.DRTIOAuxControllerAxi(core.link_layer)) coreaux = cdr(aux_controller.DRTIOAuxControllerBare(core.link_layer))
setattr(self.submodules, coreaux_name, coreaux) setattr(self.submodules, coreaux_name, coreaux)
self.csr_devices.append(coreaux_name) self.csr_devices.append(coreaux_name)
memory_address = self.mem_map["drtioaux"] + 0x800*i memory_address, size = self.axi2csr.add_memory(coreaux.transmitter.mem, read_only=False)
self.register_mem(memory_name, memory_address, 0x800, coreaux.bus) # rcv in upper half of the memory, thus added second
self.axi2csr.add_memory(coreaux.receiver.mem, read_only=False)
# and registered in PS interface
# manually, because software refers to rx/tx by halves of entire memory block, not names
self.add_memory_region(memory_name, self.mem_map["csr"] + memory_address, size * 2)
self.rustc_cfg["has_drtio"] = None self.rustc_cfg["has_drtio"] = None
# it does not have drtio routing support! # it does not have drtio routing support!
self.add_csr_group("drtioaux", drtioaux_csr_group) self.add_csr_group("drtioaux", drtioaux_csr_group)