M-Labs
/
artiq-zynq
10
1
Fork 19
Code Issues 14 Pull Requests 2 Releases Wiki Activity

satman: removed jcdg completely

This commit is contained in:
mwojcik 2021-07-23 11:00:48 +02:00
parent 7b25bc710e
commit d309409a84
2 changed files with 9 additions and 219 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

139
src/satman/jdcg.rs
View File

@ -1,139 +0,0 @@
pub mod jesd {
use libboard_artiqzynq::pl::csr;
use libboard_zynq::timer::GlobalTimer;
pub fn reset(reset: bool) {
unsafe {
csr::jesd_crg::jreset_write(if reset {1} else {0});
}
}
pub fn enable(dacno: u8, en: bool) {
unsafe {
(csr::JDCG[dacno as usize].jesd_control_enable_write)(if en {1} else {0})
}
}
pub fn phy_done(dacno: u8) -> bool {
unsafe {
(csr::JDCG[dacno as usize].jesd_control_phy_done_read)() != 0
}
}
pub fn ready(dacno: u8) -> bool {
unsafe {
(csr::JDCG[dacno as usize].jesd_control_ready_read)() != 0
}
}
pub fn prbs(dacno: u8, en: bool, timer: GlobalTimer) {
unsafe {
(csr::JDCG[dacno as usize].jesd_control_prbs_config_write)(if en {0b01} else {0b00})
}
timer.delay_us(5000);
}
pub fn stpl(dacno: u8, en: bool, timer: GlobalTimer) {
unsafe {
(csr::JDCG[dacno as usize].jesd_control_stpl_enable_write)(if en {1} else {0})
}
timer.delay_us(5000);
}
pub fn jsync(dacno: u8) -> bool {
unsafe {
(csr::JDCG[dacno as usize].jesd_control_jsync_read)() != 0
}
}
}
pub mod jdac {
use libboard_artiqzynq::{pl::csr, drtioaux};
use libboard_zynq::timer::GlobalTimer;
use super::jesd;
use super::super::jdac_common;
pub fn basic_request(dacno: u8, reqno: u8, param: u8) -> Result<u8, &'static str> {
if let Err(e) = drtioaux::send(1, &drtioaux::Packet::JdacBasicRequest {
destination: 0,
dacno: dacno,
reqno: reqno,
param: param
}) {
error!("aux packet error ({})", e);
return Err("aux packet error while sending for JESD DAC basic request");
}
match drtioaux::recv_timeout(1, Some(1000)) {
Ok(drtioaux::Packet::JdacBasicReply { succeeded, retval }) => {
if succeeded {
Ok(retval)
} else {
error!("JESD DAC basic request failed (dacno={}, reqno={})", dacno, reqno);
Err("remote error status to JESD DAC basic request")
}
},
Ok(packet) => {
error!("received unexpected aux packet: {:?}", packet);
Err("unexpected aux packet in reply to JESD DAC basic request")
},
Err(e) => {
error!("aux packet error ({})", e);
Err("aux packet error while waiting for JESD DAC basic reply")
}
}
}
pub fn init(timer: GlobalTimer) -> Result<(), &'static str> {
for dacno in 0..csr::JDCG.len() {
let dacno = dacno as u8;
info!("DAC-{} initializing...", dacno);
jesd::enable(dacno, true);
timer.delay_us(10_000);
if !jesd::phy_done(dacno) {
error!("JESD core PHY not done");
return Err("JESD core PHY not done");
}
basic_request(dacno, jdac_common::INIT, 0)?;
// JESD ready depends on JSYNC being valid, so DAC init needs to happen first
if !jesd::ready(dacno) {
error!("JESD core reported not ready, sending DAC status print request");
basic_request(dacno, jdac_common::PRINT_STATUS, 0)?;
return Err("JESD core reported not ready");
}
jesd::prbs(dacno, true);
basic_request(dacno, jdac_common::PRBS, 0)?;
jesd::prbs(dacno, false);
basic_request(dacno, jdac_common::INIT, 0)?;
timer.delay_us(5000);
if !jesd::jsync(dacno) {
error!("JESD core reported bad SYNC");
return Err("JESD core reported bad SYNC");
}
info!(" ...done initializing");
}
Ok(())
}
pub fn stpl(timer: GlobalTimer) -> Result<(), &'static str> {
for dacno in 0..csr::JDCG.len() {
let dacno = dacno as u8;
info!("Running STPL test on DAC-{}...", dacno);
jesd::stpl(dacno, true, timer);
basic_request(dacno, jdac_common::STPL, 0)?;
jesd::stpl(dacno, false, timer);
info!(" ...done STPL test");
}
Ok(())
}
}

89
src/satman/main.rs
View File

@ -6,19 +6,13 @@ extern crate log;
use core::convert::TryFrom;
use board_misoc::{csr, irq, ident, clock, i2c}; // <- port, use libboard_zynq
use libboard_zynq::timer::GlobalTimer;
#[cfg(has_si5324)]
use libboard_artiqzynq::si5324;
#[cfg(has_wrpll)]
use board_artiq::wrpll; // <- port
use board_artiq::spi; // <- port?, use libboard_zynq (if spi available/necessary)
use libboard_artiqzynq::{drtio_routing drtioaux};
use libboard_artiqzynq::logger;
use libboard_artiqzynq::{drtio_routing, drtioaux, logger};
mod repeater;
#[cfg(has_jdcg)]
mod jdcg;
#[cfg(has_jdcg)]
pub mod jdac_common;
fn drtiosat_reset(reset: bool) {
unsafe {
@ -414,7 +408,7 @@ const SI5324_SETTINGS: si5324::FrequencySettings
#[no_mangle]
pub extern fn main() -> i32 {
clock::init();
let mut timer = GlobalTimer::start();
let buffer_logger = unsafe {
logger::BufferLogger::new(&mut LOG_BUFFER[..])
@ -427,7 +421,8 @@ pub extern fn main() -> i32 {
info!("gateware ident {}", ident::read(&mut [0; 64]));
#[cfg(has_i2c)]
i2c::init().expect("I2C initialization failed");
i2c::init().expect("I2C initialization failed"); // port
//see if below is applicable (probably not - not kasli)
#[cfg(all(soc_platform = "kasli", hw_rev = "v2.0"))]
let (mut io_expander0, mut io_expander1);
#[cfg(all(soc_platform = "kasli", hw_rev = "v2.0"))]
@ -436,17 +431,6 @@ pub extern fn main() -> i32 {
io_expander1 = board_misoc::io_expander::IoExpander::new(1);
io_expander0.init().expect("I2C I/O expander #0 initialization failed");
io_expander1.init().expect("I2C I/O expander #1 initialization failed");
#[cfg(has_wrpll)]
{
io_expander0.set_oe(1, 1 << 7).unwrap();
io_expander0.set(1, 7, true);
io_expander0.service().unwrap();
io_expander1.set_oe(0, 1 << 7).unwrap();
io_expander1.set_oe(1, 1 << 7).unwrap();
io_expander1.set(0, 7, true);
io_expander1.set(1, 7, true);
io_expander1.service().unwrap();
}
// Actively drive TX_DISABLE to false on SFP0..3
io_expander0.set_oe(0, 1 << 1).unwrap();
@ -461,21 +445,19 @@ pub extern fn main() -> i32 {
io_expander1.service().unwrap();
}
//this part was commented in runtime
#[cfg(has_si5324)]
si5324::setup(&SI5324_SETTINGS, si5324::Input::Ckin1).expect("cannot initialize Si5324");
#[cfg(has_wrpll)]
wrpll::init();
unsafe {
csr::drtio_transceiver::stable_clkin_write(1);
}
clock::spin_us(1500); // wait for CPLL/QPLL lock
#[cfg(not(has_jdcg))]
timer.delay_us(1500); // wait for CPLL/QPLL lock
// #[cfg(not(has_jdcg))]
unsafe {
csr::drtio_transceiver::txenable_write(0xffffffffu32 as _);
}
#[cfg(has_wrpll)]
wrpll::diagnostics();
init_rtio_crg();
#[cfg(has_drtio_routing)]
@ -491,11 +473,6 @@ pub extern fn main() -> i32 {
let mut hardware_tick_ts = 0;
loop {
#[cfg(has_jdcg)]
unsafe {
// Hide from uplink until RTM is ready
csr::drtio_transceiver::txenable_write(0xfffffffeu32 as _);
}
while !drtiosat_link_rx_up() {
drtiosat_process_errors();
for mut rep in repeaters.iter_mut() {
@ -515,15 +492,11 @@ pub extern fn main() -> i32 {
si5324::siphaser::select_recovered_clock(true).expect("failed to switch clocks");
si5324::siphaser::calibrate_skew().expect("failed to calibrate skew");
}
#[cfg(has_wrpll)]
wrpll::select_recovered_clock(true);
drtioaux::reset(0);
drtiosat_reset(false);
drtiosat_reset_phy(false);
#[cfg(has_jdcg)]
let mut was_up = false;
while drtiosat_link_rx_up() {
drtiosat_process_errors();
process_aux_packets(&mut repeaters, &mut routing_table, &mut rank);
@ -538,18 +511,6 @@ pub extern fn main() -> i32 {
hardware_tick(&mut hardware_tick_ts);
if drtiosat_tsc_loaded() {
info!("TSC loaded from uplink");
#[cfg(has_jdcg)]
{
// We assume that the RTM on repeater0 is up.
// Uplink should not send a TSC load command unless the link is
// up, and we are hiding when the RTM is down.
if let Err(e) = jdcg::jesd204sync::sysref_rtio_align() {
error!("failed to align SYSREF with TSC ({})", e);
}
if let Err(e) = jdcg::jesd204sync::resync_dacs() {
error!("DAC resync failed after SYSREF/TSC realignment ({})", e);
}
}
for rep in repeaters.iter() {
if let Err(e) = rep.sync_tsc() {
error!("failed to sync TSC ({})", e);
@ -559,46 +520,14 @@ pub extern fn main() -> i32 {
error!("aux packet error: {}", e);
}
}
#[cfg(has_jdcg)]
{
let is_up = repeaters[0].is_up();
if is_up && !was_up {
/*
* One side of the JESD204 elastic buffer is clocked by the jitter filter
* (Si5324 or WRPLL), the other by the RTM.
* The elastic buffer can operate only when those two clocks are derived from
* the same oscillator.
* This is the case when either of those conditions is true:
* (1) The DRTIO master and the RTM are clocked directly from a common external
* source, *and* the jitter filter has locked to the recovered clock.
* This clocking scheme may provide less noise and phase drift at the DACs.
* (2) The RTM clock is connected to the jitter filter output.
* To handle those cases, we simply keep the JESD204 core in reset unless the
* jitter filter is locked to the recovered clock.
*/
jdcg::jesd::reset(false);
let _ = jdcg::jdac::init();
jdcg::jesd204sync::sysref_auto_align();
jdcg::jdac::stpl();
unsafe {
csr::drtio_transceiver::txenable_write(0xffffffffu32 as _); // unhide
}
}
was_up = is_up;
}
}
#[cfg(has_jdcg)]
jdcg::jesd::reset(true);
drtiosat_reset_phy(true);
drtiosat_reset(true);
drtiosat_tsc_loaded();
info!("uplink is down, switching to local oscillator clock");
#[cfg(has_si5324)]
si5324::siphaser::select_recovered_clock(false).expect("failed to switch clocks");
#[cfg(has_wrpll)]
wrpll::select_recovered_clock(false);
}
}