From cff2caa88f9687d0ac874746faac25294360021b Mon Sep 17 00:00:00 2001 From: mwojcik Date: Thu, 16 Feb 2023 15:09:16 +0800 Subject: [PATCH] zc706: support for 100mhz with new clocking system --- src/gateware/zc706.py | 23 +++++++++++++---------- 1 file changed, 13 insertions(+), 10 deletions(-) diff --git a/src/gateware/zc706.py b/src/gateware/zc706.py index 732ba37..0a174ae 100755 --- a/src/gateware/zc706.py +++ b/src/gateware/zc706.py @@ -42,16 +42,17 @@ class SMAClkinForward(Module): class CLK200BootstrapClock(Module): - def __init__(self, platform): + def __init__(self, platform, freq=125e6): self.clock_domains.cd_bootstrap = ClockDomain(reset_less=True) self.cd_bootstrap.clk.attr.add("keep") - clk200 = platform.request("clk200") clk200_se = Signal() pll_fb = Signal() - pll_clk125 = Signal() + pll_clkout = Signal() + assert freq in [125e6, 100e6] + divide = int(1e9/freq) self.specials += [ Instance("IBUFDS", i_I=clk200.p, i_IB=clk200.n, o_O=clk200_se), @@ -64,10 +65,10 @@ class CLK200BootstrapClock(Module): # VCO @ 1GHz p_CLKFBOUT_MULT=5, p_DIVCLK_DIVIDE=1, - # 125MHz for bootstrap - p_CLKOUT1_DIVIDE=8, p_CLKOUT1_PHASE=0.0, o_CLKOUT1=pll_clk125, + # 125MHz/100MHz for bootstrap + p_CLKOUT1_DIVIDE=divide, p_CLKOUT1_PHASE=0.0, o_CLKOUT1=pll_clkout, ), - Instance("BUFG", i_I=pll_clk125, o_O=self.cd_bootstrap.clk) + Instance("BUFG", i_I=pll_clkout, o_O=self.cd_bootstrap.clk) ] @@ -234,12 +235,13 @@ class _MasterBase(SoCCore): txout_buf = Signal() gtx0 = self.drtio_transceiver.gtxs[0] self.specials += Instance("BUFG", i_I=gtx0.txoutclk, o_O=txout_buf) - self.submodules.bootstrap = CLK200BootstrapClock(platform) + self.submodules.bootstrap = CLK200BootstrapClock(platform, clk_freq) self.submodules.sys_crg = zynq_clocking.SYSCRG( self.platform, self.ps7, txout_buf, - clk_sw=gtx0.tx_init.done) + clk_sw=gtx0.tx_init.done, + freq=clk_freq) platform.add_false_path_constraints( self.bootstrap.cd_bootstrap.clk, self.sys_crg.cd_sys.clk) self.csr_devices.append("sys_crg") @@ -373,12 +375,13 @@ class _SatelliteBase(SoCCore): "BUFG", i_I=gtx0.txoutclk, o_O=txout_buf) - self.submodules.bootstrap = CLK200BootstrapClock(platform) + self.submodules.bootstrap = CLK200BootstrapClock(platform, clk_freq) self.submodules.sys_crg = zynq_clocking.SYSCRG( self.platform, self.ps7, txout_buf, - clk_sw=gtx0.tx_init.done) + clk_sw=gtx0.tx_init.done, + freq=clk_freq) platform.add_false_path_constraints( self.bootstrap.cd_bootstrap.clk, self.sys_crg.cd_sys.clk) self.csr_devices.append("sys_crg")