M-Labs/artiq-zynq
10
1
Fork 19
Code Issues 12 Pull Requests Releases Wiki Activity

wrpll runtime: reduce mmcm output jitter

Browse Source 
rtio_clocking: update mmcm setting to use HIGH bandwidth
This commit is contained in:
morgan 2024-04-26 15:42:21 +08:00 committed by sb10q
parent 2bbaea3ad5
commit cca23aa2a5
1 changed files with 7 additions and 7 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

14
src/runtime/src/rtio_clocking.rs
View File

@ -278,8 +278,8 @@ fn wrpll_setup(timer: &mut GlobalTimer, clk: RtioClock, si549_settings: &si549::
lock_reg2: 0x7c01, lock_reg2: 0x7c01,
lock_reg3: 0xffe9, lock_reg3: 0xffe9,
power_reg: 0x9900, power_reg: 0x9900,
filt_reg1: 0x0808, filt_reg1: 0x1008,
filt_reg2: 0x0800, filt_reg2: 0x8800,
}, },
false, false,
), ),
@ -295,8 +295,8 @@ fn wrpll_setup(timer: &mut GlobalTimer, clk: RtioClock, si549_settings: &si549::
lock_reg2: 0x7c01, lock_reg2: 0x7c01,
lock_reg3: 0xffe9, lock_reg3: 0xffe9,
power_reg: 0x9900, power_reg: 0x9900,
filt_reg1: 0x0808, filt_reg1: 0x9908,
filt_reg2: 0x9800, filt_reg2: 0x8100,
}, },
false, false,
), ),
@ -312,8 +312,8 @@ fn wrpll_setup(timer: &mut GlobalTimer, clk: RtioClock, si549_settings: &si549::
lock_reg2: 0x7c01, lock_reg2: 0x7c01,
lock_reg3: 0xffe9, lock_reg3: 0xffe9,
power_reg: 0x9900, power_reg: 0x9900,
filt_reg1: 0x0808, filt_reg1: 0x9108,
filt_reg2: 0x9800, filt_reg2: 0x0100,
}, },
false, false,
), ),
@ -329,7 +329,7 @@ fn wrpll_setup(timer: &mut GlobalTimer, clk: RtioClock, si549_settings: &si549::
lock_reg2: 0x7001, lock_reg2: 0x7001,
lock_reg3: 0xf3e9, lock_reg3: 0xf3e9,
power_reg: 0x0100, power_reg: 0x0100,
filt_reg1: 0x0808, filt_reg1: 0x9908,
filt_reg2: 0x1100, filt_reg2: 0x1100,
}, },
true, true,