M-Labs/artiq-zynq
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rtio_clocking: added si5324 bypass

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mwojcik 2021-10-25 14:16:32 +08:00
parent 61442b3775
commit c94582ccbe
1 changed files with 10 additions and 3 deletions
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13
src/runtime/src/rtio_clocking.rs
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@ -35,6 +35,7 @@ fn get_rtio_clock_cfg(cfg: &Config) -> RtioClock {
} }
} }
else { else {
info!("error reading configuration. Using default internal 125MHz clock");
RtioClock::Int_125 RtioClock::Int_125
} }
} }
@ -105,16 +106,22 @@ fn setup_si5324(timer: &mut GlobalTimer, clk: RtioClock) {
crystal_ref: true crystal_ref: true
}); });
} }
let si5324_ref_input = si5324::Input::Ckin2;
si5324::setup(unsafe { (&mut i2c::I2C_BUS).as_mut().unwrap() }, si5324::setup(unsafe { (&mut i2c::I2C_BUS).as_mut().unwrap() },
&si5324_settings.unwrap(), si5324::Input::Ckin2, timer).expect("cannot initialize Si5324"); &si5324_settings.unwrap(), si5324_ref_input, timer).expect("cannot initialize Si5324");
} }
pub fn init(timer: &mut GlobalTimer, cfg: &Config) { pub fn init(timer: &mut GlobalTimer, cfg: &Config) {
let clk = get_rtio_clock_cfg(cfg); let clk = get_rtio_clock_cfg(cfg);
#[cfg(has_si5324)] #[cfg(has_si5324)]
setup_si5324(timer, clk); {
let si5324_ext_input = si5324::Input::Ckin2;
match clk {
RtioClock::Ext0_Bypass => si5324::bypass(si5324_ext_input).expect("cannot bypass Si5324"),
_ => setup_si5324(timer, clk),
}
}
#[cfg(has_drtio)] #[cfg(has_drtio)]
init_drtio(timer); init_drtio(timer);