diff --git a/src/gateware/kasli_soc.py b/src/gateware/kasli_soc.py
index e774e63..c573274 100755
--- a/src/gateware/kasli_soc.py
+++ b/src/gateware/kasli_soc.py
@@ -26,20 +26,11 @@ import acpki
 import drtio_aux_controller
 
 class SYSCRG(Module, AutoCSR):
-    def __init__(self, platform):
+    def __init__(self, platform, main_clk):
         self.pll_locked = CSRStatus()
         self.clock_domains.cd_sys = ClockDomain()
         self.clock_domains.cd_sys4x = ClockDomain(reset_less=True)
 
-        clk_synth = platform.request("cdr_clk_clean_fabric")
-        clk_synth_se = Signal()
-        platform.add_period_constraint(clk_synth.p, 8.0)
-        self.specials += [
-            Instance("IBUFGDS",
-                p_DIFF_TERM="TRUE", p_IBUF_LOW_PWR="FALSE",
-                i_I=clk_synth.p, i_IB=clk_synth.n, o_O=clk_synth_se),
-        ]
-
         pll_locked = Signal()
         sys_clk = Signal()
         sys4x_clk = Signal()
@@ -50,7 +41,7 @@ class SYSCRG(Module, AutoCSR):
                      p_BANDWIDTH="HIGH",
                      p_REF_JITTER1=0.001,
                      p_CLKIN1_PERIOD=8.0,
-                     i_CLKIN1=clk_synth_se,
+                     i_CLKIN1=main_clk,
                      i_CLKINSEL=1,
 
                      # VCO @ 1.5GHz when using 125MHz input
@@ -128,8 +119,17 @@ class GenericStandalone(SoCCore):
         self.rustc_cfg["has_si5324"] = None
         self.rustc_cfg["si5324_soft_reset"] = None
 
+        clk_synth = platform.request("cdr_clk_clean_fabric")
+        clk_synth_se = Signal()
+        platform.add_period_constraint(clk_synth.p, 8.0)
+        self.specials += [
+            Instance("IBUFGDS",
+                p_DIFF_TERM="TRUE", p_IBUF_LOW_PWR="FALSE",
+                i_I=clk_synth.p, i_IB=clk_synth.n, o_O=clk_synth_se),
+        ]
+
         self.crg = self.ps7 # HACK for eem_7series to find the clock
-        self.submodules.sys_crg = SYSCRG(self.platform)
+        self.submodules.sys_crg = SYSCRG(self.platform, clk_synth_se)
         self.csr_devices.append("sys_crg")
         # another hack since ps7 itself does not have cd_sys anymore
         self.crg.cd_sys = self.sys_crg.cd_sys
diff --git a/src/gateware/zc706.py b/src/gateware/zc706.py
index 9556e27..251676b 100755
--- a/src/gateware/zc706.py
+++ b/src/gateware/zc706.py
@@ -28,7 +28,7 @@ import drtio_aux_controller
 
 
 class SYSCRG(Module, AutoCSR):
-    def __init__(self, platform):
+    def __init__(self, platform, main_clk):
         self.pll_locked = CSRStatus()
         self.clock_domains.cd_sys = ClockDomain()
         self.clock_domains.cd_sys4x = ClockDomain(reset_less=True)
@@ -148,7 +148,27 @@ class ZC706(SoCCore):
             ident = "acpki_" + ident
         SoCCore.__init__(self, platform=platform, csr_data_width=32, ident=ident, ps_cd_sys=False)
 
-        self.submodules.sys_crg = SYSCRG(self.platform)
+        platform.add_extension(si5324_fmc33)
+        self.comb += platform.request("si5324_33").rst_n.eq(1)
+
+        cdr_clk = Signal()
+        cdr_clk_buf = Signal()
+        si5324_out = platform.request("si5324_clkout")
+        platform.add_period_constraint(si5324_out.p, 8.0)
+        self.specials += [
+            Instance("IBUFDS_GTE2",
+                i_I=si5324_out.p, i_IB=si5324_out.n,
+                o_O=cdr_clk,
+                p_CLKCM_CFG="0b1",
+                p_CLKRCV_TRST="0b1",
+                p_CLKSWING_CFG="0b11"),
+            Instance("BUFG", i_I=cdr_clk, o_O=cdr_clk_buf)
+        ]
+        self.rustc_cfg["has_si5324"] = None
+        self.rustc_cfg["si5324_as_synthesizer"] = None
+        self.rustc_cfg["si5324_soft_reset"] = None
+
+        self.submodules.sys_crg = SYSCRG(self.platform, cdr_clk_buf)
         self.csr_devices.append("sys_crg")
         self.platform.add_period_constraint(self.sys_crg.cd_sys.clk, 8.)