M-Labs/artiq-zynq
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satellite gateware: add rtio analyzer

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This commit is contained in:
mwojcik 2023-05-19 12:58:32 +08:00 committed by spaqin
parent 259b0ba1b7
commit c536a70890
3 changed files with 10 additions and 1 deletions
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4
src/gateware/kasli_soc.py
View File

@ -438,6 +438,10 @@ class GenericSatellite(SoCCore):
self.submodules.rtio_moninj = rtio.MonInj(self.rtio_channels)
self.csr_devices.append("rtio_moninj")
self.submodules.rtio_analyzer = analyzer.Analyzer(self.rtio_tsc, self.local_io.cri,
self.ps7.s_axi_hp1)
self.csr_devices.append("rtio_analyzer")
rtio_clk_period = 1e9/clk_freq
self.rustc_cfg["rtio_frequency"] = str(clk_freq/1e6)

4
src/gateware/zc706.py
View File

@ -486,6 +486,10 @@ class _SatelliteBase(SoCCore):
enable_routing=True)
self.csr_devices.append("cri_con")
self.submodules.rtio_analyzer = analyzer.Analyzer(self.rtio_tsc, self.rtio_core.cri,
self.ps7.s_axi_hp1)
self.csr_devices.append("rtio_analyzer")
self.submodules.routing_table = rtio.RoutingTableAccess(self.cri_con)
self.csr_devices.append("routing_table")

3
src/satman/src/main.rs
View File

@ -28,6 +28,7 @@ use libboard_artiq::io_expander;
#[cfg(has_si5324)]
use libboard_artiq::si5324;
use libboard_artiq::{drtio_routing, drtioaux, identifier_read, logger, pl::csr};
use libboard_artiq::{drtioaux_proto::ANALYZER_MAX_SIZE};
#[cfg(feature = "target_kasli_soc")]
use libboard_zynq::error_led::ErrorLED;
use libboard_zynq::{gic, i2c::I2c, mpcore, print, println, stdio, time::Milliseconds, timer::GlobalTimer};
@ -421,7 +422,7 @@ fn process_aux_packet(
drtioaux::send(0, &drtioaux::Packet::AnalyzerHeader {
total_byte_count: header.total_byte_count,
sent_bytes: header.sent_bytes,
overflow_occurred: header.overflow,
overflow_occurred: header.error,
})
}
drtioaux::Packet::AnalyzerDataRequest { destination: _destination } => {