From 8be5048cd342bdba3c083ab7ff6b3bdb3b397dd1 Mon Sep 17 00:00:00 2001 From: mwojcik Date: Mon, 29 Nov 2021 11:17:59 +0800 Subject: [PATCH 1/3] upgrade to new clock configuration system (#152) As mentioned in https://github.com/m-labs/artiq/issues/1735 - this is the Zynq version. Reviewed-on: https://git.m-labs.hk/M-Labs/artiq-zynq/pulls/152 Co-authored-by: mwojcik Co-committed-by: mwojcik --- README.md | 2 +- src/gateware/kasli_soc.py | 7 +- src/runtime/src/main.rs | 84 +----------- src/runtime/src/rtio_clocking.rs | 224 +++++++++++++++++++++++++++++++ 4 files changed, 233 insertions(+), 84 deletions(-) create mode 100644 src/runtime/src/rtio_clocking.rs diff --git a/README.md b/README.md index fdae0d7..eb0f98f 100644 --- a/README.md +++ b/README.md @@ -24,7 +24,7 @@ The following configuration keys are available: - ``ip``: IPv4 address. - ``ip6``: IPv6 address. - ``startup``: startup kernel in ELF format (as produced by ``artiq_compile``). -- ``rtioclk``: source of RTIO clock; valid values are ``external`` and ``internal``. +- ``rtio_clock``: source of RTIO clock; valid values are ``ext0_bypass`` and ``int_125``. - ``boot``: SD card "boot.bin" file, for replacing the boot firmware/gateware. Write only. Configurations can be read/written/removed via ``artiq_coremgmt``. Config erase is diff --git a/src/gateware/kasli_soc.py b/src/gateware/kasli_soc.py index fa45fe8..da376ea 100755 --- a/src/gateware/kasli_soc.py +++ b/src/gateware/kasli_soc.py @@ -113,8 +113,8 @@ class GenericStandalone(SoCCore): platform.add_platform_command("create_clock -name clk_fpga_0 -period 8 [get_pins \"PS7/FCLKCLK[0]\"]") platform.add_platform_command("set_input_jitter clk_fpga_0 0.24") - self.rustc_cfg["HAS_SI5324"] = None - self.rustc_cfg["SI5324_SOFT_RESET"] = None + self.rustc_cfg["has_si5324"] = None + self.rustc_cfg["si5324_soft_reset"] = None self.crg = self.ps7 # HACK for eem_7series to find the clock self.submodules.rtio_crg = RTIOCRG(self.platform) @@ -393,6 +393,9 @@ class GenericSatellite(SoCCore): self.add_memory_group("drtioaux_mem", drtioaux_memory_group) self.add_csr_group("drtiorep", drtiorep_csr_group) + self.rustc_cfg["has_si5324"] = None + self.rustc_cfg["si5324_soft_reset"] = None + if self.acpki: self.rustc_cfg["ki_impl"] = "acp" self.submodules.rtio = acpki.KernelInitiator(self.rtio_tsc, diff --git a/src/runtime/src/main.rs b/src/runtime/src/main.rs index 973afbe..da93f3f 100644 --- a/src/runtime/src/main.rs +++ b/src/runtime/src/main.rs @@ -18,12 +18,9 @@ use libasync::{task, block_async}; use libsupport_zynq::ram; use nb; use void::Void; -use embedded_hal::blocking::delay::DelayMs; use libconfig::Config; use libcortex_a9::l2c::enable_l2_cache; use libboard_artiq::{logger, identifier_read, init_gateware, pl}; -#[cfg(has_si5324)] -use libboard_artiq::si5324; mod proto_async; mod comms; @@ -35,6 +32,7 @@ mod rtio; #[path = "rtio_acp.rs"] mod rtio; mod rtio_mgt; +mod rtio_clocking; mod kernel; mod moninj; mod eh_artiq; @@ -44,65 +42,6 @@ mod analyzer; mod irq; mod i2c; -fn init_rtio(timer: &mut GlobalTimer, _cfg: &Config) { - #[cfg(has_rtio_crg_clock_sel)] - let clock_sel = - if let Ok(rtioclk) = _cfg.read_str("rtioclk") { - match rtioclk.as_ref() { - "internal" => { - info!("using internal RTIO clock"); - 0 - }, - "external" => { - info!("using external RTIO clock"); - 1 - }, - other => { - warn!("RTIO clock specification '{}' not recognized", other); - info!("using internal RTIO clock"); - 0 - }, - } - } else { - info!("using internal RTIO clock (default)"); - 0 - }; - - loop { - unsafe { - pl::csr::rtio_crg::pll_reset_write(1); - #[cfg(has_rtio_crg_clock_sel)] - pl::csr::rtio_crg::clock_sel_write(clock_sel); - pl::csr::rtio_crg::pll_reset_write(0); - } - timer.delay_ms(1); - let locked = unsafe { pl::csr::rtio_crg::pll_locked_read() != 0 }; - if locked { - info!("RTIO PLL locked"); - break; - } else { - warn!("RTIO PLL failed to lock, retrying..."); - timer.delay_ms(500); - } - } - - unsafe { - pl::csr::rtio_core::reset_phy_write(1); - } -} - -#[cfg(has_drtio)] -fn init_drtio(timer: &mut GlobalTimer) -{ - unsafe { - pl::csr::drtio_transceiver::stable_clkin_write(1); - } - timer.delay_ms(2); // wait for CPLL/QPLL lock - unsafe { - pl::csr::drtio_transceiver::txenable_write(0xffffffffu32 as _); - } -} - fn wait_for_async_rtio_error() -> nb::Result<(), Void> { unsafe { @@ -136,19 +75,7 @@ async fn report_async_rtio_errors() { } } -#[cfg(has_si5324)] -// 125MHz output, from crystal, 7 Hz -const SI5324_SETTINGS: si5324::FrequencySettings - = si5324::FrequencySettings { - n1_hs : 10, - nc1_ls : 4, - n2_hs : 10, - n2_ls : 19972, - n31 : 4565, - n32 : 4565, - bwsel : 4, - crystal_ref: true -}; + static mut LOG_BUFFER: [u8; 1<<17] = [0; 1<<17]; @@ -173,9 +100,6 @@ pub fn main_core0() { info!("detected gateware: {}", identifier_read(&mut [0; 64])); i2c::init(); - #[cfg(has_si5324)] - si5324::setup(unsafe { (&mut i2c::I2C_BUS).as_mut().unwrap() }, - &SI5324_SETTINGS, si5324::Input::Ckin2, &mut timer).expect("cannot initialize Si5324"); let cfg = match Config::new() { Ok(cfg) => cfg, @@ -185,10 +109,8 @@ pub fn main_core0() { } }; - #[cfg(has_drtio)] - init_drtio(&mut timer); + rtio_clocking::init(&mut timer, &cfg); - init_rtio(&mut timer, &cfg); task::spawn(report_async_rtio_errors()); comms::main(timer, cfg); diff --git a/src/runtime/src/rtio_clocking.rs b/src/runtime/src/rtio_clocking.rs new file mode 100644 index 0000000..a3e2f7b --- /dev/null +++ b/src/runtime/src/rtio_clocking.rs @@ -0,0 +1,224 @@ +use log::{info, warn}; +use libboard_zynq::timer::GlobalTimer; +use embedded_hal::blocking::delay::DelayMs; +use libconfig::Config; +use libboard_artiq::pl; +#[cfg(has_si5324)] +use libboard_zynq::i2c::I2c; +#[cfg(has_si5324)] +use crate::i2c; +#[cfg(has_si5324)] +use libboard_artiq::si5324; + +#[derive(Debug, PartialEq, Copy, Clone)] +#[allow(non_camel_case_types)] +pub enum RtioClock { + Default, + Int_125, + Int_100, + Int_150, + Ext0_Bypass, + Ext0_Synth0_10to125, + Ext0_Synth0_100to125, + Ext0_Synth0_125to125, +} + +fn get_rtio_clock_cfg(cfg: &Config) -> RtioClock { + let mut res = RtioClock::Default; + if let Ok(clk) = cfg.read_str("rtio_clock") { + res = match clk.as_ref() { + "int_125" => RtioClock::Int_125, + "int_100" => RtioClock::Int_100, + "int_150" => RtioClock::Int_150, + "ext0_bypass" => RtioClock::Ext0_Bypass, + "ext0_bypass_125" => RtioClock::Ext0_Bypass, + "ext0_bypass_100" => RtioClock::Ext0_Bypass, + "ext0_synth0_10to125" => RtioClock::Ext0_Synth0_10to125, + "ext0_synth0_100to125" => RtioClock::Ext0_Synth0_100to125, + "ext0_synth0_125to125" => RtioClock::Ext0_Synth0_125to125, + _ => { + warn!("Unrecognised rtio_clock setting. Falling back to default."); + RtioClock::Default + } + }; + } + else { + warn!("error reading configuration. Falling back to default."); + } + if res == RtioClock::Default { + warn!("Using default configuration - internal 125MHz RTIO clock."); + return RtioClock::Int_125; + } + res +} + + +fn init_rtio(timer: &mut GlobalTimer, _clk: RtioClock) { + #[cfg(has_rtio_crg_clock_sel)] + let clock_sel = match _clk { + RtioClock::Ext0_Bypass => { + info!("Using bypassed external clock"); + 1 + }, + RtioClock::Int_125 => { + info!("Using internal RTIO clock"); + 0 + }, + _ => { + warn!("rtio_clock setting '{:?}' is not supported. Using default internal RTIO clock instead", _clk); + 0 + } + }; + + loop { + unsafe { + pl::csr::rtio_crg::pll_reset_write(1); + #[cfg(has_rtio_crg_clock_sel)] + pl::csr::rtio_crg::clock_sel_write(clock_sel); + pl::csr::rtio_crg::pll_reset_write(0); + } + timer.delay_ms(1); + let locked = unsafe { pl::csr::rtio_crg::pll_locked_read() != 0 }; + if locked { + info!("RTIO PLL locked"); + break; + } else { + warn!("RTIO PLL failed to lock, retrying..."); + timer.delay_ms(500); + } + } + + unsafe { + pl::csr::rtio_core::reset_phy_write(1); + } +} + +#[cfg(has_drtio)] +fn init_drtio(timer: &mut GlobalTimer) +{ + unsafe { + pl::csr::drtio_transceiver::stable_clkin_write(1); + } + timer.delay_ms(2); // wait for CPLL/QPLL lock + unsafe { + pl::csr::drtio_transceiver::txenable_write(0xffffffffu32 as _); + } +} + +#[cfg(has_si5324)] +fn setup_si5324(i2c: &mut I2c, timer: &mut GlobalTimer, clk: RtioClock) { + let si5324_settings = match clk { + RtioClock::Ext0_Synth0_10to125 => { // 125 MHz output from 10 MHz CLKINx reference, 504 Hz BW + info!("using 10MHz reference to make 125MHz RTIO clock with PLL"); + si5324::FrequencySettings { + n1_hs : 10, + nc1_ls : 4, + n2_hs : 10, + n2_ls : 300, + n31 : 6, + n32 : 6, + bwsel : 4, + crystal_ref: false + } + }, + RtioClock::Ext0_Synth0_100to125 => { // 125MHz output, from 100MHz CLKINx reference, 586 Hz loop bandwidth + info!("using 10MHz reference to make 125MHz RTIO clock with PLL"); + si5324::FrequencySettings { + n1_hs : 10, + nc1_ls : 4, + n2_hs : 10, + n2_ls : 260, + n31 : 52, + n32 : 52, + bwsel : 4, + crystal_ref: false + } + }, + RtioClock::Ext0_Synth0_125to125 => { // 125MHz output, from 125MHz CLKINx reference, 606 Hz loop bandwidth + info!("using 10MHz reference to make 125MHz RTIO clock with PLL"); + si5324::FrequencySettings { + n1_hs : 5, + nc1_ls : 8, + n2_hs : 7, + n2_ls : 360, + n31 : 63, + n32 : 63, + bwsel : 4, + crystal_ref: false + } + }, + RtioClock::Int_150 => { // 150MHz output, from crystal + info!("using internal 150MHz RTIO clock"); + si5324::FrequencySettings { + n1_hs : 9, + nc1_ls : 4, + n2_hs : 10, + n2_ls : 33732, + n31 : 7139, + n32 : 7139, + bwsel : 3, + crystal_ref: true + } + }, + RtioClock::Int_100 => { // 100MHz output, from crystal. + info!("using internal 100MHz RTIO clock"); + si5324::FrequencySettings { + n1_hs : 9, + nc1_ls : 6, + n2_hs : 10, + n2_ls : 33732, + n31 : 7139, + n32 : 7139, + bwsel : 3, + crystal_ref: true + } + }, + RtioClock::Int_125 => { // 125MHz output, from crystal, 7 Hz + info!("using internal 125MHz RTIO clock"); + si5324::FrequencySettings { + n1_hs : 10, + nc1_ls : 4, + n2_hs : 10, + n2_ls : 19972, + n31 : 4565, + n32 : 4565, + bwsel : 4, + crystal_ref: true + } + } + _ => { // same setting as Int_125, but fallback to default + warn!("rtio_clock setting '{:?}' is unsupported. Falling back to default internal 125MHz RTIO clock.", clk); + si5324::FrequencySettings { + n1_hs : 10, + nc1_ls : 4, + n2_hs : 10, + n2_ls : 19972, + n31 : 4565, + n32 : 4565, + bwsel : 4, + crystal_ref: true + } + } + }; + let si5324_ref_input = si5324::Input::Ckin2; + si5324::setup(i2c, &si5324_settings, si5324_ref_input, timer).expect("cannot initialize Si5324"); +} + +pub fn init(timer: &mut GlobalTimer, cfg: &Config) { + + let clk = get_rtio_clock_cfg(cfg); + #[cfg(has_si5324)] + { + let i2c = unsafe { (&mut i2c::I2C_BUS).as_mut().unwrap() }; + let si5324_ext_input = si5324::Input::Ckin2; + match clk { + RtioClock::Ext0_Bypass => si5324::bypass(i2c, si5324_ext_input, timer).expect("cannot bypass Si5324"), + _ => setup_si5324(i2c, timer, clk), + } + } + #[cfg(has_drtio)] + init_drtio(timer); + + init_rtio(timer, clk); + +} \ No newline at end of file From ada3f2e70400f9b8be519690c92b64de01128260 Mon Sep 17 00:00:00 2001 From: mwojcik Date: Mon, 29 Nov 2021 12:27:27 +0800 Subject: [PATCH 2/3] drtio: reading still needs work buffer after all --- src/gateware/zc706.py | 2 +- src/libboard_artiq/src/drtioaux.rs | 19 +++++++++++-------- src/libboard_artiq/src/drtioaux_async.rs | 12 +++++++----- 3 files changed, 19 insertions(+), 14 deletions(-) diff --git a/src/gateware/zc706.py b/src/gateware/zc706.py index aceb2e9..eb077f4 100755 --- a/src/gateware/zc706.py +++ b/src/gateware/zc706.py @@ -399,7 +399,7 @@ class _SatelliteBase(SoCCore): self.submodules.siphaser = SiPhaser7Series( si5324_clkin=platform.request("si5324_clkin"), rx_synchronizer=self.rx_synchronizer, - ultrascale=False, + ultrascale=True, rtio_clk_freq=self.drtio_transceiver.rtio_clk_freq) platform.add_false_path_constraints( self.ps7.cd_sys.clk, self.siphaser.mmcm_freerun_output) diff --git a/src/libboard_artiq/src/drtioaux.rs b/src/libboard_artiq/src/drtioaux.rs index f147a66..4971502 100644 --- a/src/libboard_artiq/src/drtioaux.rs +++ b/src/libboard_artiq/src/drtioaux.rs @@ -1,7 +1,6 @@ use crc; use core_io::{ErrorKind as IoErrorKind, Error as IoError}; -use core::slice; use io::{proto::ProtoRead, proto::ProtoWrite, Cursor}; use libboard_zynq::{timer::GlobalTimer, time::Milliseconds}; use crate::mem::mem::DRTIOAUX_MEM; @@ -58,13 +57,14 @@ pub fn has_rx_error(linkno: u8) -> bool { } } -pub fn copy_work_buffer(src: *mut u32, dst: *mut u32, len: isize) { +pub fn copy_work_buffer(src: *mut u16, dst: *mut u16, len: isize) { // AXI writes must be 4-byte aligned (drtio proto doesn't care for that), - // and AXI burst writes are not implemented yet in gateware + // and AXI burst reads/writes are not implemented yet in gateware // thus the need for a work buffer for transmitting and copying it over unsafe { - for i in 0..(len/4) { + for i in (0..(len/2)).step_by(2) { *dst.offset(i) = *src.offset(i); + *dst.offset(i+1) = *src.offset(i+1); } } } @@ -75,9 +75,12 @@ fn receive(linkno: u8, f: F) -> Result, Error> let linkidx = linkno as usize; unsafe { if (DRTIOAUX[linkidx].aux_rx_present_read)() == 1 { - let ptr = (DRTIOAUX_MEM[linkidx].base + DRTIOAUX_MEM[linkidx].size / 2) as *mut u8; + let ptr = (DRTIOAUX_MEM[linkidx].base + DRTIOAUX_MEM[linkidx].size / 2) as *mut u16; let len = (DRTIOAUX[linkidx].aux_rx_length_read)() as usize; - let result = f(slice::from_raw_parts(ptr as *mut u8, len as usize)); + // work buffer to accomodate axi burst reads + let mut buf: [u8; 1024] = [0; 1024]; + copy_work_buffer(ptr, buf.as_mut_ptr() as *mut u16, len as isize); + let result = f(&buf[0..len]); (DRTIOAUX[linkidx].aux_rx_present_write)(1); Ok(Some(result?)) } else { @@ -130,12 +133,12 @@ fn transmit(linkno: u8, f: F) -> Result<(), Error> let linkno = linkno as usize; unsafe { while (DRTIOAUX[linkno].aux_tx_read)() != 0 {} - let ptr = DRTIOAUX_MEM[linkno].base as *mut u32; + let ptr = DRTIOAUX_MEM[linkno].base as *mut u16; let len = DRTIOAUX_MEM[linkno].size / 2; // work buffer, works with unaligned mem access let mut buf: [u8; 1024] = [0; 1024]; let len = f(&mut buf[0..len])?; - copy_work_buffer(buf.as_mut_ptr() as *mut u32, ptr, len as isize); + copy_work_buffer(buf.as_mut_ptr() as *mut u16, ptr, len as isize); (DRTIOAUX[linkno].aux_tx_length_write)(len as u16); (DRTIOAUX[linkno].aux_tx_write)(1); Ok(()) diff --git a/src/libboard_artiq/src/drtioaux_async.rs b/src/libboard_artiq/src/drtioaux_async.rs index ae069bc..cab9791 100644 --- a/src/libboard_artiq/src/drtioaux_async.rs +++ b/src/libboard_artiq/src/drtioaux_async.rs @@ -1,7 +1,6 @@ use crc; use core_io::{ErrorKind as IoErrorKind, Error as IoError}; -use core::slice; use void::Void; use nb; @@ -43,9 +42,12 @@ async fn receive(linkno: u8, f: F) -> Result, Error> let linkidx = linkno as usize; unsafe { if (DRTIOAUX[linkidx].aux_rx_present_read)() == 1 { - let ptr = (DRTIOAUX_MEM[linkidx].base + DRTIOAUX_MEM[linkidx].size / 2) as *mut u8; + let ptr = (DRTIOAUX_MEM[linkidx].base + DRTIOAUX_MEM[linkidx].size / 2) as *mut u16; let len = (DRTIOAUX[linkidx].aux_rx_length_read)() as usize; - let result = f(slice::from_raw_parts(ptr as *mut u8, len as usize)); + // work buffer to accomodate axi burst reads + let mut buf: [u8; 1024] = [0; 1024]; + copy_work_buffer(ptr, buf.as_mut_ptr() as *mut u16, len as isize); + let result = f(&buf[0..len]); (DRTIOAUX[linkidx].aux_rx_present_write)(1); Ok(Some(result?)) } else { @@ -104,12 +106,12 @@ async fn transmit(linkno: u8, f: F) -> Result<(), Error> let linkno = linkno as usize; unsafe { let _ = block_async!(tx_ready(linkno)).await; - let ptr = DRTIOAUX_MEM[linkno].base as *mut u32; + let ptr = DRTIOAUX_MEM[linkno].base as *mut u16; let len = DRTIOAUX_MEM[linkno].size / 2; // work buffer, works with unaligned mem access let mut buf: [u8; 1024] = [0; 1024]; let len = f(&mut buf[0..len])?; - copy_work_buffer(buf.as_mut_ptr() as *mut u32, ptr, len as isize); + copy_work_buffer(buf.as_mut_ptr() as *mut u16, ptr, len as isize); (DRTIOAUX[linkno].aux_tx_length_write)(len as u16); (DRTIOAUX[linkno].aux_tx_write)(1); Ok(()) From e045837b67c6469aaf35d06dca56baf1c2b8e02f Mon Sep 17 00:00:00 2001 From: mwojcik Date: Mon, 29 Nov 2021 12:48:45 +0800 Subject: [PATCH 3/3] zc706: not actually ultrascale --- src/gateware/zc706.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/gateware/zc706.py b/src/gateware/zc706.py index eb077f4..aceb2e9 100755 --- a/src/gateware/zc706.py +++ b/src/gateware/zc706.py @@ -399,7 +399,7 @@ class _SatelliteBase(SoCCore): self.submodules.siphaser = SiPhaser7Series( si5324_clkin=platform.request("si5324_clkin"), rx_synchronizer=self.rx_synchronizer, - ultrascale=True, + ultrascale=False, rtio_clk_freq=self.drtio_transceiver.rtio_clk_freq) platform.add_false_path_constraints( self.ps7.cd_sys.clk, self.siphaser.mmcm_freerun_output)