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Hydra zc706-acpki_nist_clock_satellite_100mhz-firmware Hydra build #196431 of artiq:zynq-beta:zc706-acpki_nist_clock_satellite_100mhz-firmware
Hydra zc706-acpki_nist_qc2-firmware Hydra build #196436 of artiq:zynq-beta:zc706-acpki_nist_qc2-firmware
Hydra ebaz4205-base-gateware Hydra build #196393 of artiq:zynq-beta:ebaz4205-base-gateware
Hydra zc706-acpki_nist_clock-firmware Hydra build #196411 of artiq:zynq-beta:zc706-acpki_nist_clock-firmware
Hydra zc706-nist_clock_satellite_100mhz-gateware Hydra build #196489 of artiq:zynq-beta:zc706-nist_clock_satellite_100mhz-gateware
Hydra zc706-acpki_nist_clock_satellite_100mhz-gateware Hydra build #196433 of artiq:zynq-beta:zc706-acpki_nist_clock_satellite_100mhz-gateware
Hydra zc706-acpki_nist_clock_master-firmware Hydra build #196416 of artiq:zynq-beta:zc706-acpki_nist_clock_master-firmware
Hydra zc706-acpki_nist_clock_master_100mhz-firmware Hydra build #196421 of artiq:zynq-beta:zc706-acpki_nist_clock_master_100mhz-firmware
Hydra zc706-acpki_nist_qc2_master_100mhz-gateware Hydra build #196448 of artiq:zynq-beta:zc706-acpki_nist_qc2_master_100mhz-gateware
Hydra zc706-nist_qc2_satellite-gateware Hydra build #196509 of artiq:zynq-beta:zc706-nist_qc2_satellite-gateware
Hydra zc706-acpki_nist_qc2_satellite-gateware Hydra build #196453 of artiq:zynq-beta:zc706-acpki_nist_qc2_satellite-gateware
Hydra zc706-acpki_nist_clock_satellite-firmware Hydra build #196426 of artiq:zynq-beta:zc706-acpki_nist_clock_satellite-firmware
Hydra zc706-nist_qc2-gateware Hydra build #196494 of artiq:zynq-beta:zc706-nist_qc2-gateware
Hydra zc706-acpki_nist_qc2_master-firmware Hydra build #196441 of artiq:zynq-beta:zc706-acpki_nist_qc2_master-firmware
Hydra zc706-nist_qc2_master-gateware Hydra build #196499 of artiq:zynq-beta:zc706-nist_qc2_master-gateware
Hydra zc706-acpki_nist_qc2_master_100mhz-firmware Hydra build #196446 of artiq:zynq-beta:zc706-acpki_nist_qc2_master_100mhz-firmware
Hydra zc706-acpki_nist_qc2_satellite-firmware Hydra build #196451 of artiq:zynq-beta:zc706-acpki_nist_qc2_satellite-firmware
Hydra zc706-nist_qc2_master_100mhz-gateware Hydra build #196504 of artiq:zynq-beta:zc706-nist_qc2_master_100mhz-gateware
Hydra zc706-acpki_nist_qc2_satellite_100mhz-firmware Hydra build #196456 of artiq:zynq-beta:zc706-acpki_nist_qc2_satellite_100mhz-firmware
Hydra zc706-cxp_4r_fmc-firmware Hydra build #196461 of artiq:zynq-beta:zc706-cxp_4r_fmc-firmware
Hydra zc706-acpki_nist_qc2-gateware Hydra build #196438 of artiq:zynq-beta:zc706-acpki_nist_qc2-gateware
Hydra zc706-nist_qc2-firmware Hydra build #196492 of artiq:zynq-beta:zc706-nist_qc2-firmware
Hydra zc706-nist_clock-firmware Hydra build #196467 of artiq:zynq-beta:zc706-nist_clock-firmware
Hydra zc706-nist_clock_master-firmware Hydra build #196472 of artiq:zynq-beta:zc706-nist_clock_master-firmware
Hydra zc706-acpki_nist_clock-gateware Hydra build #196413 of artiq:zynq-beta:zc706-acpki_nist_clock-gateware
Hydra zc706-nist_clock_master_100mhz-firmware Hydra build #196477 of artiq:zynq-beta:zc706-nist_clock_master_100mhz-firmware
Hydra zc706-nist_clock_satellite-firmware Hydra build #196482 of artiq:zynq-beta:zc706-nist_clock_satellite-firmware
Hydra zc706-acpki_nist_clock_master-gateware Hydra build #196418 of artiq:zynq-beta:zc706-acpki_nist_clock_master-gateware
Hydra zc706-nist_clock_satellite_100mhz-firmware Hydra build #196487 of artiq:zynq-beta:zc706-nist_clock_satellite_100mhz-firmware
Hydra zc706-acpki_nist_clock_master_100mhz-gateware Hydra build #196423 of artiq:zynq-beta:zc706-acpki_nist_clock_master_100mhz-gateware
Hydra zc706-nist_qc2_master-firmware Hydra build #196497 of artiq:zynq-beta:zc706-nist_qc2_master-firmware
Hydra zc706-nist_qc2_satellite-firmware Hydra build #196507 of artiq:zynq-beta:zc706-nist_qc2_satellite-firmware
Hydra zc706-acpki_nist_clock_satellite-gateware Hydra build #196428 of artiq:zynq-beta:zc706-acpki_nist_clock_satellite-gateware
Hydra zc706-nist_qc2_master_100mhz-firmware Hydra build #196502 of artiq:zynq-beta:zc706-nist_qc2_master_100mhz-firmware
Hydra zc706-acpki_nist_qc2_master-gateware Hydra build #196443 of artiq:zynq-beta:zc706-acpki_nist_qc2_master-gateware
Hydra zc706-nist_clock-gateware Hydra build #196469 of artiq:zynq-beta:zc706-nist_clock-gateware
Hydra zc706-cxp_4r_fmc-gateware Hydra build #196463 of artiq:zynq-beta:zc706-cxp_4r_fmc-gateware
Hydra zc706-nist_qc2_satellite_100mhz-firmware Hydra build #196512 of artiq:zynq-beta:zc706-nist_qc2_satellite_100mhz-firmware
Hydra ebaz4205-base-firmware Hydra build #196392 of artiq:zynq-beta:ebaz4205-base-firmware
Hydra zc706-acpki_nist_qc2_satellite_100mhz-gateware Hydra build #196458 of artiq:zynq-beta:zc706-acpki_nist_qc2_satellite_100mhz-gateware
Hydra kasli_soc-demo-firmware Hydra build #196398 of artiq:zynq-beta:kasli_soc-demo-firmware
Hydra zc706-acpki_nist_qc2-jtag Hydra build #196439 of artiq:zynq-beta:zc706-acpki_nist_qc2-jtag
Hydra zc706-nist_qc2-jtag Hydra build #196495 of artiq:zynq-beta:zc706-nist_qc2-jtag
Hydra fmt-check Hydra build #196396 of artiq:zynq-beta:fmt-check
Hydra kasli_soc-satellite-firmware Hydra build #196406 of artiq:zynq-beta:kasli_soc-satellite-firmware
Hydra zc706-acpki_nist_clock-fsbl-sd Hydra build #196412 of artiq:zynq-beta:zc706-acpki_nist_clock-fsbl-sd
Hydra zc706-acpki_nist_clock-jtag Hydra build #196414 of artiq:zynq-beta:zc706-acpki_nist_clock-jtag
Hydra zc706-acpki_nist_clock-sd Hydra build #196415 of artiq:zynq-beta:zc706-acpki_nist_clock-sd
Hydra zc706-acpki_nist_clock_satellite-sd Hydra build #196430 of artiq:zynq-beta:zc706-acpki_nist_clock_satellite-sd
Hydra zc706-acpki_nist_clock_satellite_100mhz-fsbl-sd Hydra build #196432 of artiq:zynq-beta:zc706-acpki_nist_clock_satellite_100mhz-fsbl-sd
Hydra zc706-acpki_nist_clock_satellite_100mhz-jtag Hydra build #196434 of artiq:zynq-beta:zc706-acpki_nist_clock_satellite_100mhz-jtag
Hydra zc706-acpki_nist_clock_satellite_100mhz-sd Hydra build #196435 of artiq:zynq-beta:zc706-acpki_nist_clock_satellite_100mhz-sd
Hydra kasli_soc-master-firmware Hydra build #196402 of artiq:zynq-beta:kasli_soc-master-firmware
Hydra ebaz4205-base-jtag Hydra build #196394 of artiq:zynq-beta:ebaz4205-base-jtag
Hydra ebaz4205-base-sd Hydra build #196395 of artiq:zynq-beta:ebaz4205-base-sd
Hydra zc706-acpki_nist_clock_master-fsbl-sd Hydra build #196417 of artiq:zynq-beta:zc706-acpki_nist_clock_master-fsbl-sd
Hydra zc706-acpki_nist_clock_master-jtag Hydra build #196419 of artiq:zynq-beta:zc706-acpki_nist_clock_master-jtag
Hydra zc706-acpki_nist_clock_master-sd Hydra build #196420 of artiq:zynq-beta:zc706-acpki_nist_clock_master-sd
Hydra zc706-acpki_nist_clock_master_100mhz-fsbl-sd Hydra build #196422 of artiq:zynq-beta:zc706-acpki_nist_clock_master_100mhz-fsbl-sd
Hydra gateware-sim Hydra build #196397 of artiq:zynq-beta:gateware-sim
Hydra zc706-acpki_nist_clock_master_100mhz-jtag Hydra build #196424 of artiq:zynq-beta:zc706-acpki_nist_clock_master_100mhz-jtag
Hydra zc706-acpki_nist_clock_master_100mhz-sd Hydra build #196425 of artiq:zynq-beta:zc706-acpki_nist_clock_master_100mhz-sd
Hydra zc706-acpki_nist_clock_satellite-fsbl-sd Hydra build #196427 of artiq:zynq-beta:zc706-acpki_nist_clock_satellite-fsbl-sd
Hydra zc706-acpki_nist_clock_satellite-jtag Hydra build #196429 of artiq:zynq-beta:zc706-acpki_nist_clock_satellite-jtag
Hydra zc706-acpki_nist_qc2-fsbl-sd Hydra build #196437 of artiq:zynq-beta:zc706-acpki_nist_qc2-fsbl-sd
Hydra zc706-acpki_nist_qc2-sd Hydra build #196440 of artiq:zynq-beta:zc706-acpki_nist_qc2-sd
Hydra zc706-acpki_nist_qc2_master_100mhz-fsbl-sd Hydra build #196447 of artiq:zynq-beta:zc706-acpki_nist_qc2_master_100mhz-fsbl-sd
Hydra zc706-nist_clock-fsbl-sd Hydra build #196468 of artiq:zynq-beta:zc706-nist_clock-fsbl-sd
Hydra zc706-nist_clock-jtag Hydra build #196470 of artiq:zynq-beta:zc706-nist_clock-jtag
Hydra zc706-nist_clock-sd Hydra build #196471 of artiq:zynq-beta:zc706-nist_clock-sd
Hydra zc706-nist_clock_satellite_100mhz-fsbl-sd Hydra build #196488 of artiq:zynq-beta:zc706-nist_clock_satellite_100mhz-fsbl-sd
Hydra zc706-nist_clock_satellite_100mhz-jtag Hydra build #196490 of artiq:zynq-beta:zc706-nist_clock_satellite_100mhz-jtag
Hydra zc706-nist_clock_satellite_100mhz-sd Hydra build #196491 of artiq:zynq-beta:zc706-nist_clock_satellite_100mhz-sd
Hydra zc706-nist_qc2-fsbl-sd Hydra build #196493 of artiq:zynq-beta:zc706-nist_qc2-fsbl-sd
Hydra zc706-acpki_nist_qc2_master-fsbl-sd Hydra build #196442 of artiq:zynq-beta:zc706-acpki_nist_qc2_master-fsbl-sd
Hydra zc706-acpki_nist_qc2_master-jtag Hydra build #196444 of artiq:zynq-beta:zc706-acpki_nist_qc2_master-jtag
Hydra zc706-acpki_nist_qc2_master-sd Hydra build #196445 of artiq:zynq-beta:zc706-acpki_nist_qc2_master-sd
Hydra zc706-acpki_nist_qc2_master_100mhz-jtag Hydra build #196449 of artiq:zynq-beta:zc706-acpki_nist_qc2_master_100mhz-jtag
Hydra zc706-acpki_nist_qc2_master_100mhz-sd Hydra build #196450 of artiq:zynq-beta:zc706-acpki_nist_qc2_master_100mhz-sd
Hydra zc706-acpki_nist_qc2_satellite-fsbl-sd Hydra build #196452 of artiq:zynq-beta:zc706-acpki_nist_qc2_satellite-fsbl-sd
Hydra zc706-acpki_nist_qc2_satellite-jtag Hydra build #196454 of artiq:zynq-beta:zc706-acpki_nist_qc2_satellite-jtag
Hydra zc706-acpki_nist_qc2_satellite-sd Hydra build #196455 of artiq:zynq-beta:zc706-acpki_nist_qc2_satellite-sd
Hydra zc706-acpki_nist_qc2_satellite_100mhz-fsbl-sd Hydra build #196457 of artiq:zynq-beta:zc706-acpki_nist_qc2_satellite_100mhz-fsbl-sd
Hydra zc706-acpki_nist_qc2_satellite_100mhz-jtag Hydra build #196459 of artiq:zynq-beta:zc706-acpki_nist_qc2_satellite_100mhz-jtag
Hydra zc706-acpki_nist_qc2_satellite_100mhz-sd Hydra build #196460 of artiq:zynq-beta:zc706-acpki_nist_qc2_satellite_100mhz-sd
Hydra zc706-cxp_4r_fmc-fsbl-sd Hydra build #196462 of artiq:zynq-beta:zc706-cxp_4r_fmc-fsbl-sd
Hydra zc706-cxp_4r_fmc-jtag Hydra build #196464 of artiq:zynq-beta:zc706-cxp_4r_fmc-jtag
Hydra zc706-cxp_4r_fmc-sd Hydra build #196465 of artiq:zynq-beta:zc706-cxp_4r_fmc-sd
Hydra zc706-nist_qc2-sd Hydra build #196496 of artiq:zynq-beta:zc706-nist_qc2-sd
Hydra zc706-nist_qc2_master-fsbl-sd Hydra build #196498 of artiq:zynq-beta:zc706-nist_qc2_master-fsbl-sd
Hydra zc706-nist_qc2_master-jtag Hydra build #196500 of artiq:zynq-beta:zc706-nist_qc2_master-jtag
Hydra zc706-nist_qc2_master-sd Hydra build #196501 of artiq:zynq-beta:zc706-nist_qc2_master-sd
Hydra zc706-nist_qc2_master_100mhz-fsbl-sd Hydra build #196503 of artiq:zynq-beta:zc706-nist_qc2_master_100mhz-fsbl-sd
Hydra zc706-nist_qc2_master_100mhz-jtag Hydra build #196505 of artiq:zynq-beta:zc706-nist_qc2_master_100mhz-jtag
Hydra zc706-nist_qc2_master_100mhz-sd Hydra build #196506 of artiq:zynq-beta:zc706-nist_qc2_master_100mhz-sd
Hydra zc706-nist_qc2_satellite-fsbl-sd Hydra build #196508 of artiq:zynq-beta:zc706-nist_qc2_satellite-fsbl-sd
Hydra zc706-nist_qc2_satellite-jtag Hydra build #196510 of artiq:zynq-beta:zc706-nist_qc2_satellite-jtag
Hydra zc706-nist_qc2_satellite-sd Hydra build #196511 of artiq:zynq-beta:zc706-nist_qc2_satellite-sd
Hydra zc706-acpki-hitl-tests Hydra build #196410 of artiq:zynq-beta:zc706-acpki-hitl-tests
Hydra zc706-nist_clock_master-gateware Hydra build #196474 of artiq:zynq-beta:zc706-nist_clock_master-gateware
Hydra zc706-nist_clock_master-jtag Hydra build #196475 of artiq:zynq-beta:zc706-nist_clock_master-jtag
Hydra zc706-nist_clock_master-fsbl-sd Hydra build #196473 of artiq:zynq-beta:zc706-nist_clock_master-fsbl-sd
Hydra zc706-nist_clock_master-sd Hydra build #196476 of artiq:zynq-beta:zc706-nist_clock_master-sd
Hydra zc706-nist_clock_master_100mhz-gateware Hydra build #196479 of artiq:zynq-beta:zc706-nist_clock_master_100mhz-gateware
Hydra zc706-hitl-tests Hydra build #196466 of artiq:zynq-beta:zc706-hitl-tests
Hydra zc706-nist_clock_master_100mhz-jtag Hydra build #196480 of artiq:zynq-beta:zc706-nist_clock_master_100mhz-jtag
Hydra zc706-nist_clock_master_100mhz-fsbl-sd Hydra build #196478 of artiq:zynq-beta:zc706-nist_clock_master_100mhz-fsbl-sd
Hydra zc706-nist_clock_master_100mhz-sd Hydra build #196481 of artiq:zynq-beta:zc706-nist_clock_master_100mhz-sd
Hydra zc706-nist_qc2_satellite_100mhz-jtag Hydra build #196515 of artiq:zynq-beta:zc706-nist_qc2_satellite_100mhz-jtag
Hydra zc706-nist_qc2_satellite_100mhz-fsbl-sd Hydra build #196513 of artiq:zynq-beta:zc706-nist_qc2_satellite_100mhz-fsbl-sd
Hydra zc706-nist_qc2_satellite_100mhz-sd Hydra build #196516 of artiq:zynq-beta:zc706-nist_qc2_satellite_100mhz-sd
Hydra kasli_soc-demo-gateware Hydra build #196399 of artiq:zynq-beta:kasli_soc-demo-gateware
Hydra kasli_soc-demo-jtag Hydra build #196400 of artiq:zynq-beta:kasli_soc-demo-jtag
Hydra kasli_soc-demo-sd Hydra build #196401 of artiq:zynq-beta:kasli_soc-demo-sd
Hydra kasli_soc-master-gateware Hydra build #196403 of artiq:zynq-beta:kasli_soc-master-gateware
Hydra kasli_soc-master-jtag Hydra build #196404 of artiq:zynq-beta:kasli_soc-master-jtag
Hydra kasli_soc-master-sd Hydra build #196405 of artiq:zynq-beta:kasli_soc-master-sd
Hydra zc706-nist_clock_satellite-gateware Hydra build #196484 of artiq:zynq-beta:zc706-nist_clock_satellite-gateware
Hydra zc706-nist_clock_satellite-jtag Hydra build #196485 of artiq:zynq-beta:zc706-nist_clock_satellite-jtag
Hydra zc706-nist_clock_satellite-sd Hydra build #196486 of artiq:zynq-beta:zc706-nist_clock_satellite-sd
Hydra zc706-nist_clock_satellite-fsbl-sd Hydra build #196483 of artiq:zynq-beta:zc706-nist_clock_satellite-fsbl-sd
Hydra zc706-nist_qc2_satellite_100mhz-gateware Hydra build #196514 of artiq:zynq-beta:zc706-nist_qc2_satellite_100mhz-gateware
Hydra kasli_soc-satellite-gateware Hydra build #196407 of artiq:zynq-beta:kasli_soc-satellite-gateware
Hydra kasli_soc-satellite-jtag Hydra build #196408 of artiq:zynq-beta:kasli_soc-satellite-jtag
Hydra kasli_soc-satellite-sd Hydra build #196409 of artiq:zynq-beta:kasli_soc-satellite-sd

This commit was merged in pull request #464.
This commit is contained in:
2026-03-30 08:31:00 +02:00
parent 43c5591d04
commit c049e80ecc
43 changed files with 198 additions and 213 deletions

1
.gitignore vendored
View File

@@ -11,3 +11,4 @@ src/libio/Cargo.toml
src/libksupport/Cargo.toml
src/runtime/Cargo.toml
src/satman/Cargo.toml
src/target

14
flake.lock generated
View File

@@ -265,11 +265,11 @@
]
},
"locked": {
"lastModified": 1773630837,
"narHash": "sha256-zJhgAGnbVKeBMJOb9ctZm4BGS/Rnrz+5lfSXTVah4HQ=",
"lastModified": 1774408260,
"narHash": "sha256-Jn9d9r85dmf3gTMnSRt6t+DP2nQ5uJns/MMXg2FpzfM=",
"owner": "oxalica",
"repo": "rust-overlay",
"rev": "f600ea449c7b5bb596fa1cf21c871cc5b9e31316",
"rev": "d6471ee5a8f470251e6e5b83a20a182eb6c46c9b",
"type": "github"
},
"original": {
@@ -360,11 +360,11 @@
"rust-overlay": "rust-overlay_2"
},
"locked": {
"lastModified": 1773657038,
"narHash": "sha256-sPYsZbYhT6kGTq3ljlt2YYejJ/3U3a9zVGGuChnQGpg=",
"lastModified": 1774605290,
"narHash": "sha256-KSNifNiLciMPqp3xTlpX2QIfEjAExkZEYDmBW6A3mEE=",
"ref": "refs/heads/master",
"rev": "df53e57a10a518de2652b1aa1c94d793187a8ab0",
"revCount": 747,
"rev": "830af9feb0a0fc94ebd29a7dad017c54d879f97a",
"revCount": 755,
"type": "git",
"url": "https://git.m-labs.hk/m-labs/zynq-rs"
},

View File

@@ -10,3 +10,4 @@ target = "armv7-none-eabihf.json"
[unstable]
build-std = ["core", "alloc", "compiler_builtins"]
json-target-spec = true

36
src/Cargo.lock generated
View File

@@ -46,6 +46,12 @@ version = "1.3.2"
source = "registry+https://github.com/rust-lang/crates.io-index"
checksum = "bef38d45163c2f1dde094a7dfd33ccf595c92905c8f8f4fdc18d06fb1037718a"
[[package]]
name = "bitflags"
version = "2.11.0"
source = "registry+https://github.com/rust-lang/crates.io-index"
checksum = "843867be96c8daad0d758b57df9392b6d8d271134fce549de6ce169ff98a92af"
[[package]]
name = "build_const"
version = "0.2.2"
@@ -83,7 +89,7 @@ checksum = "baf1de4339761588bc0619e3cbc0120ee582ebb74b53b4efbf79117bd2da40fd"
[[package]]
name = "core_io"
version = "0.1.0"
source = "git+https://git.m-labs.hk/M-Labs/rs-core_io.git?rev=e9d3edf027#e9d3edf0272502b0dd6c26e8a4869c2912657615"
source = "git+https://git.m-labs.hk/AQT/rs-core_io.git?branch=update-rust#2ac9298effbe20d6f9a02adec74b92685f46af0c"
[[package]]
name = "crc"
@@ -128,14 +134,18 @@ dependencies = [
"void",
]
[[package]]
name = "embedded-io"
version = "0.7.1"
source = "registry+https://github.com/rust-lang/crates.io-index"
checksum = "9eb1aa714776b75c7e67e1da744b81a129b3ff919c8712b5e1b32252c1f07cc7"
[[package]]
name = "fatfs"
version = "0.3.6"
source = "git+https://git.m-labs.hk/M-Labs/rust-fatfs.git?rev=4b5e420084#4b5e420084fd1c4a9c105680b687523909b6469c"
version = "0.4.0"
source = "git+https://github.com/rafalh/rust-fatfs?rev=c4b8847#c4b88477b22ca7e5131fbd8891f62a5deaa88e6e"
dependencies = [
"bitflags",
"byteorder",
"core_io",
"bitflags 2.11.0",
"log",
]
@@ -217,7 +227,7 @@ name = "io"
version = "0.0.0"
dependencies = [
"byteorder",
"core_io",
"embedded-io",
"libsupport_zynq",
]
@@ -227,10 +237,10 @@ version = "0.1.0"
dependencies = [
"build_zynq",
"byteorder",
"core_io",
"cslice",
"dwarf",
"dyld",
"embedded-io",
"io",
"libasync",
"libboard_artiq",
@@ -265,9 +275,9 @@ version = "0.0.0"
dependencies = [
"build_zynq",
"byteorder",
"core_io",
"crc",
"embedded-hal",
"embedded-io",
"io",
"libasync",
"libboard_zynq",
@@ -308,7 +318,6 @@ dependencies = [
name = "libconfig"
version = "0.1.0"
dependencies = [
"core_io",
"fatfs",
"libboard_zynq",
"libcortex_a9",
@@ -511,6 +520,7 @@ dependencies = [
"dwarf",
"dyld",
"embedded-hal",
"embedded-io",
"futures",
"io",
"ksupport",
@@ -540,10 +550,10 @@ dependencies = [
"async-recursion",
"build_zynq",
"byteorder",
"core_io",
"crc",
"cslice",
"embedded-hal",
"embedded-io",
"io",
"ksupport",
"libasync",
@@ -576,7 +586,7 @@ version = "0.7.5"
source = "registry+https://github.com/rust-lang/crates.io-index"
checksum = "3e4a069bef843d170df47e7c0a8bf8d037f217d9f5b325865acc3e466ffe40d3"
dependencies = [
"bitflags",
"bitflags 1.3.2",
"byteorder",
"managed",
]
@@ -598,7 +608,7 @@ version = "0.1.8"
source = "git+https://git.m-labs.hk/M-Labs/tar-no-std?rev=2ab6dc5#2ab6dc58e5249c59c4eb03eaf3a119bcdd678d32"
dependencies = [
"arrayvec",
"bitflags",
"bitflags 1.3.2",
"log",
]

View File

@@ -14,7 +14,7 @@
"panic-strategy": "abort",
"requires-uwtable": true,
"relocation-model": "static",
"target-c-int-width": "32",
"target-c-int-width": 32,
"target-endian": "little",
"target-pointer-width": "32"
"target-pointer-width": 32
}

View File

@@ -20,13 +20,13 @@ build_zynq = { path = "../libbuild_zynq" }
log = "0.4"
log_buffer = { version = "1.2" }
crc = { version = "1.7", default-features = false }
core_io = { git = "https://git.m-labs.hk/M-Labs/rs-core_io.git", rev = "e9d3edf027", features = ["collections"] }
embedded-hal = "0.2"
embedded-io = "0.7"
nb = "1.0"
void = { version = "1", default-features = false }
byteorder = { version = "1.3", default-features = false }
io = { path = "../libio", features = ["byteorder"] }
io = { path = "../libio", features = ["alloc", "byteorder"] }
libboard_zynq = { path = "@@ZYNQ_RS@@/libboard_zynq", features = ["async"] }
libregister = { path = "@@ZYNQ_RS@@/libregister" }
libconfig = { path = "@@ZYNQ_RS@@/libconfig", features = ["fat_lfn"] }

View File

@@ -1,5 +1,3 @@
extern crate build_zynq;
fn main() {
build_zynq::cfg();
}

View File

@@ -1,8 +1,8 @@
use core::fmt;
use core::{convert::Infallible, fmt};
use byteorder::{ByteOrder, NetworkEndian};
use core_io::{Error as IoError, Read, Write};
use crc::crc32::checksum_ieee;
use embedded_io::{Read, Write};
use io::{Cursor, ProtoRead, ProtoWrite};
pub const CTRL_PACKET_MAXSIZE: usize = 128; // for compatibility with version1.x compliant Devices - Section 12.1.6 (CXP-001-2021)
@@ -12,7 +12,7 @@ pub const DATA_MAXSIZE: usize =
pub enum Error {
CorruptedPacket,
CtrlAckError(u8),
Io(IoError),
IoReadExactError(embedded_io::ReadExactError<Infallible>),
LengthOutOfRange(u32),
TagMismatch,
TimedOut,
@@ -36,7 +36,7 @@ impl fmt::Display for Error {
0x80 => write!(f, "CtrlAckError - Failed CRC test in last received command"),
_ => write!(f, "CtrlAckError - Unknown ack code {:#X}", ack_code),
},
&Error::Io(ref err) => write!(f, "IoError - {:?}", err),
&Error::IoReadExactError(ref err) => write!(f, "IoReadExactError - {:?}", err),
&Error::LengthOutOfRange(length) => write!(
f,
"LengthOutOfRange - Message length {} is not between 1 and {}",
@@ -52,9 +52,15 @@ impl fmt::Display for Error {
}
}
impl From<IoError> for Error {
fn from(value: IoError) -> Error {
Error::Io(value)
impl From<Infallible> for Error {
fn from(err: Infallible) -> Self {
match err {}
}
}
impl From<embedded_io::ReadExactError<Infallible>> for Error {
fn from(err: embedded_io::ReadExactError<Infallible>) -> Self {
Self::IoReadExactError(err)
}
}
@@ -66,7 +72,7 @@ fn get_cxp_crc(bytes: &[u8]) -> u32 {
}
trait CxpRead: Read {
fn read_exact_4x(&mut self, buf: &mut [u8]) -> Result<(), Error> {
fn read_exact_4x(&mut self, buf: &mut [u8]) -> Result<(), embedded_io::ReadExactError<Self::Error>> {
let mut temp = [0u8; 4];
for byte in buf {
// Section 9.2.2.1 (CXP-001-2021)
@@ -79,7 +85,7 @@ trait CxpRead: Read {
Ok(())
}
fn read_4x_u8(&mut self) -> Result<u8, Error> {
fn read_4x_u8(&mut self) -> Result<u8, embedded_io::ReadExactError<Self::Error>> {
let mut bytes = [0; 1];
self.read_exact_4x(&mut bytes)?;
Ok(bytes[0])
@@ -157,14 +163,14 @@ impl RXCTRLPacket {
}
trait CxpWrite: Write {
fn write_all_4x(&mut self, buf: &[u8]) -> Result<(), Error> {
fn write_all_4x(&mut self, buf: &[u8]) -> Result<(), Self::Error> {
for byte in buf {
self.write_all(&[*byte; 4])?;
}
Ok(())
}
fn write_4x_u8(&mut self, value: u8) -> Result<(), Error> {
fn write_4x_u8(&mut self, value: u8) -> Result<(), Self::Error> {
self.write_all_4x(&[value])
}
}

View File

@@ -1,7 +1,6 @@
use core::{arch::asm, slice};
use core::{arch::asm, convert::Infallible, slice};
use byteorder::NativeEndian;
use core_io::{Error as IoError, ErrorKind as IoErrorKind};
use io::{Cursor,
proto::{ProtoRead, ProtoWrite}};
use libboard_zynq::timer;
@@ -20,18 +19,24 @@ pub enum Error {
RoutingError,
Protocol(ProtocolError),
Protocol(ProtocolError<Infallible>),
}
impl From<ProtocolError> for Error {
fn from(value: ProtocolError) -> Error {
Error::Protocol(value)
impl From<ProtocolError<Infallible>> for Error {
fn from(err: ProtocolError<Infallible>) -> Self {
Error::Protocol(err)
}
}
impl From<IoError> for Error {
fn from(value: IoError) -> Error {
Error::Protocol(ProtocolError::Io(value))
impl From<Infallible> for Error {
fn from(err: Infallible) -> Self {
match err {}
}
}
impl From<embedded_io::ReadExactError<Infallible>> for Error {
fn from(err: embedded_io::ReadExactError<Infallible>) -> Self {
Error::Protocol(ProtocolError::IoReadExactError(err))
}
}
@@ -65,8 +70,8 @@ pub fn has_rx_error(linkno: usize) -> bool {
}
}
fn receive<F, T>(linkno: usize, f: F) -> Result<Option<T>, Error>
where F: FnOnce(&[u8]) -> Result<T, Error> {
fn receive<F, T, E>(linkno: usize, f: F) -> Result<Option<T>, E>
where F: FnOnce(&[u8]) -> Result<T, E> {
let linkidx = linkno as usize;
unsafe {
if (DRTIOAUX[linkidx].aux_rx_present_read)() == 1 {
@@ -88,7 +93,7 @@ pub fn recv(linkno: usize) -> Result<Option<Packet>, Error> {
receive(linkno, |buffer| {
if buffer.len() < 8 {
return Err(IoError::new(IoErrorKind::UnexpectedEof, "Unexpected end").into());
return Err(embedded_io::ReadExactError::UnexpectedEof.into());
}
let mut reader = Cursor::new(buffer);
@@ -117,8 +122,8 @@ pub fn recv_timeout(linkno: usize, timeout_ms: Option<u64>) -> Result<Packet, Er
Err(Error::TimedOut)
}
fn transmit<F>(linkno: usize, f: F) -> Result<(), Error>
where F: FnOnce(&mut [u8]) -> Result<usize, Error> {
fn transmit<F, E>(linkno: usize, f: F) -> Result<(), E>
where F: FnOnce(&mut [u8]) -> Result<usize, E> {
unsafe {
while (DRTIOAUX[linkno].aux_tx_read)() != 0 {}
let ptr = DRTIOAUX_MEM[linkno].base as *mut u32;

View File

@@ -1,7 +1,6 @@
use core::slice;
use byteorder::NativeEndian;
use core_io::{Error as IoError, ErrorKind as IoErrorKind};
use io::{Cursor,
proto::{ProtoRead, ProtoWrite}};
use libasync::{block_async, task};
@@ -33,8 +32,8 @@ fn tx_ready(linkno: usize) -> nb::Result<(), Void> {
}
}
async fn receive<F, T>(linkno: usize, f: F) -> Result<Option<T>, Error>
where F: FnOnce(&[u8]) -> Result<T, Error> {
async fn receive<F, T, E>(linkno: usize, f: F) -> Result<Option<T>, E>
where F: FnOnce(&[u8]) -> Result<T, E> {
let linkidx = linkno as usize;
unsafe {
if (DRTIOAUX[linkidx].aux_rx_present_read)() == 1 {
@@ -56,7 +55,7 @@ pub async fn recv(linkno: usize) -> Result<Option<Packet>, Error> {
receive(linkno, |buffer| {
if buffer.len() < 8 {
return Err(IoError::new(IoErrorKind::UnexpectedEof, "Unexpected end").into());
return Err(embedded_io::ReadExactError::UnexpectedEof.into());
}
let mut reader = Cursor::new(buffer);
@@ -94,8 +93,8 @@ pub async fn recv_timeout(linkno: usize, timeout_ms: Option<u64>) -> Result<Pack
Err(Error::TimedOut)
}
async fn transmit<F>(linkno: usize, f: F) -> Result<(), Error>
where F: FnOnce(&mut [u8]) -> Result<usize, Error> {
async fn transmit<F, E>(linkno: usize, f: F) -> Result<(), E>
where F: FnOnce(&mut [u8]) -> Result<usize, E> {
unsafe {
let _ = block_async!(tx_ready(linkno)).await;
let ptr = DRTIOAUX_MEM[linkno].base as *mut u32;

View File

@@ -1,5 +1,4 @@
use byteorder::NativeEndian;
use core_io::Error as IoError;
use io::proto::{ProtoRead, ProtoWrite};
pub const MAX_PACKET: usize = 1024;
@@ -17,14 +16,21 @@ pub const SAT_PAYLOAD_MAX_SIZE: usize = /*max size*/
pub const MASTER_PAYLOAD_MAX_SIZE: usize = SAT_PAYLOAD_MAX_SIZE - /*source*/1 - /*destination*/1 - /*ID*/4;
#[derive(Debug)]
pub enum Error {
pub enum Error<E> {
UnknownPacket(u8),
Io(IoError),
Io(E),
IoReadExactError(embedded_io::ReadExactError<E>),
}
impl From<IoError> for Error {
fn from(value: IoError) -> Error {
Error::Io(value)
impl<E> From<E> for Error<E> {
fn from(err: E) -> Self {
Self::Io(err)
}
}
impl<E> From<embedded_io::ReadExactError<E>> for Error<E> {
fn from(err: embedded_io::ReadExactError<E>) -> Self {
Self::IoReadExactError(err)
}
}
@@ -417,7 +423,7 @@ pub enum Packet {
}
impl Packet {
pub fn read_from<R: ProtoRead>(reader: &mut R) -> Result<Self, Error> {
pub fn read_from<R: ProtoRead>(reader: &mut R) -> Result<Self, Error<R::Error>> {
Ok(match reader.read_u8()? {
0x00 => Packet::EchoRequest,
0x01 => Packet::EchoReply,
@@ -858,7 +864,7 @@ impl Packet {
})
}
pub fn write_to<W: ProtoWrite>(&self, writer: &mut W) -> Result<(), IoError> {
pub fn write_to<W: ProtoWrite>(&self, writer: &mut W) -> Result<(), Error<W::Error>> {
match *self {
Packet::EchoRequest => writer.write_u8(0x00)?,
Packet::EchoReply => writer.write_u8(0x01)?,

View File

@@ -1,20 +1,7 @@
#![no_std]
#![feature(never_type)]
#![feature(naked_functions)]
#![allow(unexpected_cfgs)]
extern crate alloc;
extern crate core_io;
extern crate crc;
extern crate embedded_hal;
extern crate io;
extern crate libasync;
extern crate libboard_zynq;
extern crate libconfig;
extern crate libcortex_a9;
extern crate libregister;
extern crate log;
extern crate log_buffer;
pub mod drtio_routing;
#[cfg(has_drtio)]

View File

@@ -1,8 +1,6 @@
#![no_std]
extern crate alloc;
extern crate libcortex_a9;
extern crate log;
use alloc::string::String;
use core::{convert, fmt, ops::Range, str};

View File

@@ -9,10 +9,10 @@ name = "io"
path = "lib.rs"
[dependencies]
core_io = { git = "https://git.m-labs.hk/M-Labs/rs-core_io.git", rev = "e9d3edf027", features = ["collections"] }
byteorder = { version = "1.0", default-features = false, optional = true }
embedded-io = "0.7"
libsupport_zynq = { path = "@@ZYNQ_RS@@/libsupport_zynq", default-features = false, features = ["alloc_core"] }
[features]
alloc = []
alloc = ["embedded-io/alloc"]

View File

@@ -1,9 +1,9 @@
#[cfg(feature = "alloc")]
use alloc::vec::Vec;
use core::arch::asm;
use core_io::{Error as IoError, Read, Write};
use core::{arch::asm, convert::Infallible};
// TODO: Check if `Cursor` has been added to `embedded-io` yet.
// See https://github.com/rust-embedded/embedded-hal/pull/717.
#[derive(Debug, Clone)]
pub struct Cursor<T> {
inner: T,
@@ -42,8 +42,12 @@ impl<T> Cursor<T> {
}
}
impl<T: AsRef<[u8]>> Read for Cursor<T> {
fn read(&mut self, buf: &mut [u8]) -> Result<usize, IoError> {
impl<T> embedded_io::ErrorType for Cursor<T> {
type Error = Infallible;
}
impl<T: AsRef<[u8]>> embedded_io::Read for Cursor<T> {
fn read(&mut self, buf: &mut [u8]) -> Result<usize, Self::Error> {
let data = &self.inner.as_ref()[self.pos..];
let len = buf.len().min(data.len());
// ``copy_from_slice`` generates AXI bursts, use a regular loop instead
@@ -58,8 +62,8 @@ impl<T: AsRef<[u8]>> Read for Cursor<T> {
}
}
impl Write for Cursor<&mut [u8]> {
fn write(&mut self, buf: &[u8]) -> Result<usize, IoError> {
impl embedded_io::Write for Cursor<&mut [u8]> {
fn write(&mut self, buf: &[u8]) -> Result<usize, Self::Error> {
let data = &mut self.inner[self.pos..];
let len = buf.len().min(data.len());
for i in 0..len {
@@ -73,20 +77,20 @@ impl Write for Cursor<&mut [u8]> {
}
#[inline]
fn flush(&mut self) -> Result<(), IoError> {
fn flush(&mut self) -> Result<(), Self::Error> {
Ok(())
}
}
#[cfg(feature = "alloc")]
impl Write for Cursor<Vec<u8>> {
fn write(&mut self, buf: &[u8]) -> Result<usize, IoError> {
impl embedded_io::Write for Cursor<Vec<u8>> {
fn write(&mut self, buf: &[u8]) -> Result<usize, Self::Error> {
self.inner.extend_from_slice(buf);
Ok(buf.len())
}
#[inline]
fn flush(&mut self) -> Result<(), IoError> {
fn flush(&mut self) -> Result<(), Self::Error> {
Ok(())
}
}

View File

@@ -1,12 +1,7 @@
#![no_std]
#![feature(never_type)]
#[cfg(feature = "alloc")]
extern crate alloc;
extern crate core_io;
#[cfg(feature = "byteorder")]
extern crate byteorder;
pub mod cursor;
#[cfg(feature = "byteorder")]

View File

@@ -1,9 +1,10 @@
#[cfg(feature = "alloc")]
use alloc::{string::String, vec};
#[cfg(feature = "alloc")]
use core::str::Utf8Error;
use byteorder::ByteOrder;
use core_io::{Error, Read, Write};
use embedded_io::{Read, Write};
#[cfg(feature = "alloc")]
#[derive(Debug, Clone, PartialEq)]
@@ -14,41 +15,41 @@ pub enum ReadStringError<T> {
pub trait ProtoRead: Read {
#[inline]
fn read_u8(&mut self) -> Result<u8, Error> {
fn read_u8(&mut self) -> Result<u8, embedded_io::ReadExactError<Self::Error>> {
let mut bytes = [0; 1];
self.read_exact(&mut bytes)?;
Ok(bytes[0])
}
#[inline]
fn read_u16<T: ByteOrder>(&mut self) -> Result<u16, Error> {
fn read_u16<T: ByteOrder>(&mut self) -> Result<u16, embedded_io::ReadExactError<Self::Error>> {
let mut bytes = [0; 2];
self.read_exact(&mut bytes)?;
Ok(T::read_u16(&bytes))
}
#[inline]
fn read_u32<T: ByteOrder>(&mut self) -> Result<u32, Error> {
fn read_u32<T: ByteOrder>(&mut self) -> Result<u32, embedded_io::ReadExactError<Self::Error>> {
let mut bytes = [0; 4];
self.read_exact(&mut bytes)?;
Ok(T::read_u32(&bytes))
}
#[inline]
fn read_u64<T: ByteOrder>(&mut self) -> Result<u64, Error> {
fn read_u64<T: ByteOrder>(&mut self) -> Result<u64, embedded_io::ReadExactError<Self::Error>> {
let mut bytes = [0; 8];
self.read_exact(&mut bytes)?;
Ok(T::read_u64(&bytes))
}
#[inline]
fn read_bool(&mut self) -> Result<bool, Error> {
fn read_bool(&mut self) -> Result<bool, embedded_io::ReadExactError<Self::Error>> {
Ok(self.read_u8()? != 0)
}
#[inline]
#[cfg(feature = "alloc")]
fn read_bytes<T: ByteOrder>(&mut self) -> Result<vec::Vec<u8>, Error> {
fn read_bytes<T: ByteOrder>(&mut self) -> Result<vec::Vec<u8>, embedded_io::ReadExactError<Self::Error>> {
let length = self.read_u32::<T>()?;
let mut value = vec![0; length as usize];
self.read_exact(&mut value)?;
@@ -57,7 +58,9 @@ pub trait ProtoRead: Read {
#[inline]
#[cfg(feature = "alloc")]
fn read_string<T: ByteOrder>(&mut self) -> Result<String, ReadStringError<Error>> {
fn read_string<T: ByteOrder>(
&mut self,
) -> Result<String, ReadStringError<embedded_io::ReadExactError<Self::Error>>> {
let bytes = self.read_bytes::<T>().map_err(ReadStringError::Other)?;
String::from_utf8(bytes).map_err(|err| ReadStringError::Utf8(err.utf8_error()))
}
@@ -65,73 +68,73 @@ pub trait ProtoRead: Read {
pub trait ProtoWrite: Write {
#[inline]
fn write_u8(&mut self, value: u8) -> Result<(), Error> {
fn write_u8(&mut self, value: u8) -> Result<(), Self::Error> {
let bytes = [value; 1];
self.write_all(&bytes)
}
#[inline]
fn write_i8(&mut self, value: i8) -> Result<(), Error> {
fn write_i8(&mut self, value: i8) -> Result<(), Self::Error> {
let bytes = [value as u8; 1];
self.write_all(&bytes)
}
#[inline]
fn write_u16<T: ByteOrder>(&mut self, value: u16) -> Result<(), Error> {
fn write_u16<T: ByteOrder>(&mut self, value: u16) -> Result<(), Self::Error> {
let mut bytes = [0; 2];
T::write_u16(&mut bytes, value);
self.write_all(&bytes)
}
#[inline]
fn write_i16<T: ByteOrder>(&mut self, value: i16) -> Result<(), Error> {
fn write_i16<T: ByteOrder>(&mut self, value: i16) -> Result<(), Self::Error> {
let mut bytes = [0; 2];
T::write_i16(&mut bytes, value);
self.write_all(&bytes)
}
#[inline]
fn write_u32<T: ByteOrder>(&mut self, value: u32) -> Result<(), Error> {
fn write_u32<T: ByteOrder>(&mut self, value: u32) -> Result<(), Self::Error> {
let mut bytes = [0; 4];
T::write_u32(&mut bytes, value);
self.write_all(&bytes)
}
#[inline]
fn write_i32<T: ByteOrder>(&mut self, value: i32) -> Result<(), Error> {
fn write_i32<T: ByteOrder>(&mut self, value: i32) -> Result<(), Self::Error> {
let mut bytes = [0; 4];
T::write_i32(&mut bytes, value);
self.write_all(&bytes)
}
#[inline]
fn write_u64<T: ByteOrder>(&mut self, value: u64) -> Result<(), Error> {
fn write_u64<T: ByteOrder>(&mut self, value: u64) -> Result<(), Self::Error> {
let mut bytes = [0; 8];
T::write_u64(&mut bytes, value);
self.write_all(&bytes)
}
#[inline]
fn write_i64<T: ByteOrder>(&mut self, value: i64) -> Result<(), Error> {
fn write_i64<T: ByteOrder>(&mut self, value: i64) -> Result<(), Self::Error> {
let mut bytes = [0; 8];
T::write_i64(&mut bytes, value);
self.write_all(&bytes)
}
#[inline]
fn write_bool(&mut self, value: bool) -> Result<(), Error> {
fn write_bool(&mut self, value: bool) -> Result<(), Self::Error> {
self.write_u8(value as u8)
}
#[inline]
fn write_bytes<T: ByteOrder>(&mut self, value: &[u8]) -> Result<(), Error> {
fn write_bytes<T: ByteOrder>(&mut self, value: &[u8]) -> Result<(), Self::Error> {
self.write_u32::<T>(value.len() as u32)?;
self.write_all(value)
}
#[inline]
#[cfg(feature = "alloc")]
fn write_string<T: ByteOrder>(&mut self, value: &str) -> Result<(), Error> {
fn write_string<T: ByteOrder>(&mut self, value: &str) -> Result<(), Self::Error> {
self.write_bytes::<T>(value.as_bytes())
}
}

View File

@@ -11,7 +11,7 @@ build_zynq = { path = "../libbuild_zynq" }
[dependencies]
cslice = "0.3"
log = "0.4"
core_io = { git = "https://git.m-labs.hk/M-Labs/rs-core_io.git", rev = "e9d3edf027", features = ["collections"] }
embedded-io = { version = "0.7", features = ["alloc"] }
byteorder = { version = "1.3", default-features = false }
void = { version = "1", default-features = false }
log_buffer = { version = "1.2" }

View File

@@ -1,5 +1,3 @@
extern crate build_zynq;
fn main() {
build_zynq::cfg();
}

View File

@@ -12,10 +12,9 @@
// except according to those terms.
#![allow(non_camel_case_types)]
use core::mem;
use core::{convert::Infallible, mem};
use byteorder::NativeEndian;
use core_io::Error as ReadError;
use cslice::{AsCSlice, CSlice};
use dwarf::eh::{self, EHAction, EHContext};
use io::{Cursor, ProtoRead};
@@ -302,7 +301,9 @@ pub unsafe extern "C" fn raise(exception: *const Exception) -> ! {
unreachable!();
}
fn read_exception_string<'a>(reader: &mut Cursor<&[u8]>) -> Result<CSlice<'a, u8>, ReadError> {
fn read_exception_string<'a>(
reader: &mut Cursor<&[u8]>,
) -> Result<CSlice<'a, u8>, embedded_io::ReadExactError<Infallible>> {
let len = reader.read_u32::<NativeEndian>()? as usize;
if len == usize::MAX {
let data = reader.read_u32::<NativeEndian>()?;
@@ -318,7 +319,7 @@ fn read_exception_string<'a>(reader: &mut Cursor<&[u8]>) -> Result<CSlice<'a, u8
}
}
fn read_exception(raw_exception: &[u8]) -> Result<Exception, ReadError> {
fn read_exception(raw_exception: &[u8]) -> Result<Exception<'_>, embedded_io::ReadExactError<Infallible>> {
let mut reader = Cursor::new(raw_exception);
let mut byte = reader.read_u8()?;

View File

@@ -1,5 +1,5 @@
use alloc::vec;
use core::{ffi::VaList, ptr, str};
use core::{ptr, str};
use libc::{c_char, c_int, size_t};
use log::{info, warn};
@@ -16,13 +16,13 @@ use super::{cache,
use crate::eh_artiq;
extern "C" {
fn vsnprintf_(buffer: *mut c_char, count: size_t, format: *const c_char, va: VaList) -> c_int;
fn vsnprintf_(buffer: *mut c_char, count: size_t, format: *const c_char, args: ...) -> c_int;
}
unsafe extern "C" fn core_log(fmt: *const c_char, mut args: ...) {
let size = vsnprintf_(ptr::null_mut(), 0, fmt, args.as_va_list()) as usize;
unsafe extern "C" fn core_log(fmt: *const c_char, args: ...) {
let size = vsnprintf_(ptr::null_mut(), 0, fmt, args.clone()) as usize;
let mut buf = vec![0; size + 1];
vsnprintf_(buf.as_mut_ptr() as *mut i8, size + 1, fmt, args.as_va_list());
vsnprintf_(buf.as_mut_ptr() as *mut i8, size + 1, fmt, args);
let buf: &[u8] = &buf.as_slice()[..size - 1]; // strip \n and NUL
match str::from_utf8(buf) {
Ok(s) => info!("kernel: {}", s),
@@ -33,10 +33,10 @@ unsafe extern "C" fn core_log(fmt: *const c_char, mut args: ...) {
}
}
unsafe extern "C" fn rtio_log(fmt: *const c_char, mut args: ...) {
let size = vsnprintf_(ptr::null_mut(), 0, fmt, args.as_va_list()) as usize;
unsafe extern "C" fn rtio_log(fmt: *const c_char, args: ...) {
let size = vsnprintf_(ptr::null_mut(), 0, fmt, args.clone()) as usize;
let mut buf = vec![0; size + 1];
vsnprintf_(buf.as_mut_ptr(), size + 1, fmt, args.as_va_list());
vsnprintf_(buf.as_mut_ptr(), size + 1, fmt, args);
rtio::write_log(buf.as_slice());
}

View File

@@ -5,7 +5,7 @@ use cslice::{AsCSlice, CSlice};
use super::{KERNEL_CHANNEL_0TO1, KERNEL_CHANNEL_1TO0, Message};
pub extern "C" fn get(key: CSlice<u8>) -> &CSlice<'static, i32> {
pub extern "C" fn get(key: CSlice<'_, u8>) -> &CSlice<'static, i32> {
let key = String::from_utf8(key.as_ref().to_vec()).unwrap();
unsafe {
KERNEL_CHANNEL_1TO0

View File

@@ -1,4 +1,5 @@
use alloc::{string::{String, ToString},
use alloc::{format,
string::{String, ToString},
vec::Vec};
use core::fmt;

View File

@@ -1,11 +1,8 @@
#![no_std]
#![feature(c_variadic)]
#![feature(const_btree_len)]
#![feature(naked_functions)]
#![allow(unexpected_cfgs)]
#![allow(static_mut_refs)]
#[macro_use]
extern crate alloc;
#[cfg(has_drtiosat)]

View File

@@ -1,7 +1,6 @@
use core::str;
use byteorder::{ByteOrder, NativeEndian};
use core_io::Error;
use cslice::{CMutSlice, CSlice};
use io::{ProtoRead, ProtoWrite};
use log::trace;
@@ -43,7 +42,7 @@ unsafe fn recv_elements<F, R: ProtoRead>(
length: usize,
storage: *mut (),
alloc: &mut F,
) -> Result<(), Error>
) -> Result<(), embedded_io::ReadExactError<R::Error>>
where
F: FnMut(usize) -> *mut (),
{
@@ -78,7 +77,12 @@ where
Ok(())
}
unsafe fn recv_value<F, R>(reader: &mut R, tag: Tag, data: &mut *mut (), alloc: &mut F) -> Result<(), Error>
unsafe fn recv_value<F, R>(
reader: &mut R,
tag: Tag,
data: &mut *mut (),
alloc: &mut F,
) -> Result<(), embedded_io::ReadExactError<R::Error>>
where
F: FnMut(usize) -> *mut (),
R: ProtoRead,
@@ -179,7 +183,7 @@ pub fn recv_return<'a, F, R>(
tag_bytes: &'a [u8],
data: *mut (),
alloc: &mut F,
) -> Result<&'a [u8], Error>
) -> Result<&'a [u8], embedded_io::ReadExactError<R::Error>>
where
F: FnMut(usize) -> *mut (),
R: ProtoRead,
@@ -200,7 +204,7 @@ unsafe fn send_elements<W: ProtoWrite>(
length: usize,
data: *const (),
write_tags: bool,
) -> Result<(), Error> {
) -> Result<(), W::Error> {
if write_tags {
writer.write_u8(elt_tag.as_u8())?;
}
@@ -234,7 +238,7 @@ unsafe fn send_value<W: ProtoWrite>(
tag: Tag,
data: &mut *const (),
write_tags: bool,
) -> Result<(), Error> {
) -> Result<(), W::Error> {
macro_rules! consume_value {
($ty:ty, | $ptr:ident | $map:expr) => {{
let $ptr = align_ptr::<$ty>(*data);
@@ -339,7 +343,7 @@ pub fn send_args<W: ProtoWrite>(
tag_bytes: &[u8],
data: *const *const (),
write_tags: bool,
) -> Result<(), Error> {
) -> Result<(), W::Error> {
let (arg_tags_bytes, return_tag_bytes) = split_tag(tag_bytes);
let mut args_it = TagIterator::new(arg_tags_bytes);

View File

@@ -1,7 +1,5 @@
#![no_std]
#![allow(internal_features)]
#![feature(link_cfg)]
#![cfg_attr(not(target_env = "msvc"), feature(libc))]
cfg_if::cfg_if! {
if #[cfg(target_env = "msvc")] {

View File

@@ -20,7 +20,8 @@ num-derive = "0.4"
cslice = "0.3"
log = "0.4"
embedded-hal = "0.2"
core_io = { git = "https://git.m-labs.hk/M-Labs/rs-core_io.git", rev = "e9d3edf027", features = ["collections"] }
embedded-io = "0.7"
core_io = { git = "https://git.m-labs.hk/AQT/rs-core_io.git", branch = "update-rust", features = ["collections"] }
crc = { version = "1.7", default-features = false }
byteorder = { version = "1.3", default-features = false }
void = { version = "1", default-features = false }

View File

@@ -1,5 +1,3 @@
extern crate build_zynq;
fn main() {
build_zynq::add_linker_script();
build_zynq::cfg();

View File

@@ -1,9 +1,8 @@
#[cfg(has_drtio)]
use alloc::string::ToString;
use alloc::{collections::BTreeMap, rc::Rc, string::String, vec::Vec};
use core::{cell::RefCell, fmt, slice, str};
use core::{cell::RefCell, convert::Infallible, fmt, slice, str};
use core_io::Error as IoError;
use cslice::CSlice;
use dyld::elf;
use futures::{future::FutureExt, select_biased};
@@ -55,7 +54,7 @@ use crate::{subkernel, subkernel::Error as SubkernelError};
#[derive(Debug, Clone, Copy, PartialEq, Eq)]
pub enum Error {
NetworkError(smoltcp::Error),
IoError,
IoReadExactError(embedded_io::ReadExactError<Infallible>),
UnexpectedPattern,
UnrecognizedPacket,
#[cfg(has_drtio)]
@@ -69,8 +68,8 @@ pub type Result<T> = core::result::Result<T, Error>;
impl fmt::Display for Error {
fn fmt(&self, f: &mut fmt::Formatter) -> fmt::Result {
match self {
Error::NetworkError(error) => write!(f, "network error: {}", error),
Error::IoError => write!(f, "io error"),
Error::NetworkError(err) => write!(f, "network error: {err}"),
Error::IoReadExactError(err) => write!(f, "io error: {err}"),
Error::UnexpectedPattern => write!(f, "unexpected pattern"),
Error::UnrecognizedPacket => write!(f, "unrecognized packet"),
#[cfg(has_drtio)]
@@ -87,9 +86,9 @@ impl From<smoltcp::Error> for Error {
}
}
impl From<IoError> for Error {
fn from(_error: IoError) -> Self {
Error::IoError
impl From<embedded_io::ReadExactError<Infallible>> for Error {
fn from(err: embedded_io::ReadExactError<Infallible>) -> Self {
Self::IoReadExactError(err)
}
}

View File

@@ -1,8 +1,6 @@
#![no_std]
#![no_main]
#![recursion_limit = "1024"] // for futures_util::select!
#![feature(alloc_error_handler)]
#![feature(const_btree_len)]
#![allow(internal_features)]
#![feature(lang_items)]
#![allow(unexpected_cfgs)]
@@ -13,6 +11,7 @@ extern crate alloc;
#[cfg(all(feature = "target_kasli_soc", has_virtual_leds))]
use core::cell::RefCell;
#[cfg(any(has_cxp_grabber, has_grabber, all(feature = "target_kasli_soc", has_virtual_leds)))]
use libasync::task;
#[cfg(has_drtio_eem)]
use libboard_artiq::drtio_eem;

View File

@@ -3,6 +3,7 @@ use core::{cell::RefCell, str::Utf8Error};
use byteorder::{ByteOrder, NativeEndian};
use crc::crc32;
use embedded_io::Read;
use futures::{future::poll_fn, task::Poll};
use libasync::{smoltcp::TcpStream, task};
#[cfg(has_drtio)]
@@ -131,8 +132,7 @@ async fn read_key(stream: &mut TcpStream) -> Result<String> {
#[cfg(has_drtio)]
mod remote_coremgmt {
use core_io::Read;
use io::ProtoWrite;
use io::{ProtoRead, ProtoWrite};
use libboard_artiq::{drtioaux_async,
drtioaux_proto::{MASTER_PAYLOAD_MAX_SIZE, Packet}};

View File

@@ -64,5 +64,4 @@ fn soft_panic(info: &core::panic::PanicInfo) -> ! {
}
#[lang = "eh_personality"]
#[no_mangle]
pub extern "C" fn rust_eh_personality() {}

View File

@@ -14,8 +14,7 @@ pub mod drtio {
use libasync::task;
#[cfg(has_drtio_eem)]
use libboard_artiq::drtio_eem;
use libboard_artiq::{drtioaux::Error as DrtioError,
drtioaux_async,
use libboard_artiq::{drtioaux, drtioaux_async,
drtioaux_async::Packet,
drtioaux_proto::{MASTER_PAYLOAD_MAX_SIZE, PayloadStatus},
resolve_channel_name};
@@ -65,8 +64,8 @@ pub mod drtio {
}
}
impl From<DrtioError> for Error {
fn from(_error: DrtioError) -> Self {
impl From<drtioaux::Error> for Error {
fn from(_err: drtioaux::Error) -> Self {
Error::AuxError
}
}
@@ -183,7 +182,7 @@ pub mod drtio {
}
match drtioaux_async::recv_timeout(linkno, Some(timeout)).await {
Ok(packet) => return Ok(packet),
Err(DrtioError::TimedOut) => return Err(Error::Timeout),
Err(drtioaux::Error::TimedOut) => return Err(Error::Timeout),
Err(_) => return Err(Error::AuxError),
}
}

View File

@@ -17,10 +17,10 @@ build_zynq = { path = "../libbuild_zynq" }
[dependencies]
log = { version = "0.4", default-features = false }
byteorder = { version = "1.3", default-features = false }
core_io = { git = "https://git.m-labs.hk/M-Labs/rs-core_io.git", rev = "e9d3edf027", features = ["collections"] }
crc = { version = "1.7", default-features = false }
cslice = "0.3"
embedded-hal = "0.2"
embedded-io = "0.7"
async-recursion = "1.1"
libboard_zynq = { path = "@@ZYNQ_RS@@/libboard_zynq", features = ["ipv6", "async"]}

View File

@@ -1,5 +1,3 @@
extern crate build_zynq;
fn main() {
build_zynq::add_linker_script();
build_zynq::cfg();

View File

@@ -2,6 +2,7 @@ use core::cmp::min;
use libboard_artiq::{drtioaux_proto::SAT_PAYLOAD_MAX_SIZE, pl::csr};
use libcortex_a9::cache;
use log::warn;
const BUFFER_SIZE: usize = 512 * 1024;

View File

@@ -3,6 +3,7 @@ use libboard_artiq::{drtio_routing, drtioaux, drtioaux_async,
pl::csr};
use libboard_zynq::{i2c::{Error as I2cError, I2c},
slcr, timer};
use log::{error, info, warn};
#[cfg(has_cxp_grabber)]
use crate::drtiosat_cxp;

View File

@@ -5,26 +5,8 @@
#![feature(lang_items)]
#![allow(unexpected_cfgs)]
#[macro_use]
extern crate log;
extern crate byteorder;
extern crate core_io;
extern crate crc;
extern crate cslice;
extern crate embedded_hal;
extern crate io;
extern crate ksupport;
extern crate libboard_artiq;
extern crate libboard_zynq;
extern crate libconfig;
extern crate libcortex_a9;
extern crate libregister;
extern crate libsupport_zynq;
extern crate unwind;
extern crate alloc;
extern crate unwind;
use core::cell::RefCell;
@@ -49,6 +31,7 @@ use libboard_zynq::{i2c::I2c, print, println, timer};
use libcortex_a9::{l2c::enable_l2_cache, regs::MPIDR};
use libregister::RegisterR;
use libsupport_zynq::{exception_vectors, ram};
use log::{error, info, warn};
use mgmt::Manager as CoreManager;
use routing::Router;
use subkernel::Manager as KernelManager;
@@ -596,5 +579,4 @@ pub fn panic_fmt(info: &core::panic::PanicInfo) -> ! {
}
#[lang = "eh_personality"]
#[no_mangle]
pub extern "C" fn rust_eh_personality() {}

View File

@@ -1,7 +1,6 @@
use alloc::vec::Vec;
use byteorder::{ByteOrder, NativeEndian};
use core_io::Write;
use crc::crc32;
use io::ProtoRead;
use libboard_artiq::{drtioaux_proto::SAT_PAYLOAD_MAX_SIZE,
@@ -70,7 +69,7 @@ impl Manager {
}
pub fn add_config_data(&mut self, data: &[u8], data_len: usize) {
self.config_payload.write_all(&data[..data_len]).unwrap();
self.config_payload.extend_from_slice(&data[..data_len]);
}
pub fn clear_config_data(&mut self) {

View File

@@ -5,6 +5,7 @@ use libboard_artiq::{drtio_routing, drtioaux};
use libboard_artiq::{drtioaux_async, pl::csr};
#[cfg(has_drtio_routing)]
use libboard_zynq::timer;
use log::{error, info, warn};
use crate::routing::Router;

View File

@@ -3,6 +3,7 @@ use core::cmp::min;
use libboard_artiq::{drtio_routing, drtioaux, drtioaux_async,
drtioaux_proto::{MASTER_PAYLOAD_MAX_SIZE, PayloadStatus, SAT_PAYLOAD_MAX_SIZE}};
use log::error;
pub struct SliceMeta {
pub destination: u8,

View File

@@ -2,7 +2,6 @@ use alloc::boxed::Box; // for async_recursion
use async_recursion::async_recursion;
use byteorder::{ByteOrder, NativeEndian};
use core_io::Error;
use cslice::CMutSlice;
use io::ProtoRead;
use ksupport::rpc::{tag::{Tag, TagIterator},
@@ -16,7 +15,7 @@ async unsafe fn recv_elements<R: ProtoRead>(
length: usize,
storage: *mut (),
alloc: &mut (impl AsyncFnMut(usize) -> *mut () + 'async_recursion),
) -> Result<(), Error> {
) -> Result<(), embedded_io::ReadExactError<R::Error>> {
match elt_tag {
Tag::Bool => {
let dest = core::slice::from_raw_parts_mut(storage as *mut u8, length);
@@ -54,7 +53,7 @@ async unsafe fn recv_value<R: ProtoRead>(
tag: Tag<'async_recursion>,
data: &mut *mut (),
alloc: &mut (impl AsyncFnMut(usize) -> *mut () + 'async_recursion),
) -> Result<(), Error> {
) -> Result<(), embedded_io::ReadExactError<R::Error>> {
macro_rules! consume_value {
($ty:ty, | $ptr:ident | $map:expr) => {{
let $ptr = align_ptr_mut::<$ty>(*data);
@@ -146,15 +145,12 @@ async unsafe fn recv_value<R: ProtoRead>(
}
}
pub async fn recv_return<'a, 'b, R>(
pub async fn recv_return<'a, 'b, R: ProtoRead>(
reader: &mut R,
tag_bytes: &'a [u8],
data: *mut (),
alloc: &'b mut impl AsyncFnMut(usize) -> *mut (),
) -> Result<&'a [u8], Error>
where
R: ProtoRead,
{
) -> Result<&'a [u8], embedded_io::ReadExactError<R::Error>> {
let mut it = TagIterator::new(tag_bytes);
trace!("recv ...->{}", it);

View File

@@ -2,10 +2,9 @@ use alloc::{collections::BTreeMap,
format,
string::{String, ToString},
vec::Vec};
use core::{cell::RefCell, slice, str};
use core::{cell::RefCell, convert::Infallible, slice, str};
use byteorder::NativeEndian;
use core_io::Error as IoError;
use cslice::AsCSlice;
use io::{Cursor, ProtoWrite};
use ksupport::{eh_artiq, kernel, kernel::rtio};
@@ -18,7 +17,7 @@ use libboard_artiq::{drtio_routing::RoutingTable,
pl::csr};
use libboard_zynq::timer;
use libcortex_a9::sync_channel::Receiver;
use log::warn;
use log::{error, info, warn};
use crate::{dma::{Error as DmaError, Manager as DmaManager},
routing::{Router, SliceMeta, Sliceable},
@@ -72,27 +71,27 @@ pub enum Error {
DmaError(DmaError),
}
impl From<IoError> for Error {
fn from(_value: IoError) -> Error {
Error::SubkernelIoError
impl From<embedded_io::ReadExactError<Infallible>> for Error {
fn from(_err: embedded_io::ReadExactError<Infallible>) -> Self {
Self::SubkernelIoError
}
}
impl From<DmaError> for Error {
fn from(value: DmaError) -> Error {
Error::DmaError(value)
fn from(value: DmaError) -> Self {
Self::DmaError(value)
}
}
impl From<()> for Error {
fn from(_: ()) -> Error {
Error::NoMessage
fn from(_: ()) -> Self {
Self::NoMessage
}
}
impl From<drtioaux::Error> for Error {
fn from(_value: drtioaux::Error) -> Error {
Error::DrtioError
fn from(_value: drtioaux::Error) -> Self {
Self::DrtioError
}
}
@@ -1088,7 +1087,7 @@ fn write_exception<W: ProtoWrite>(
exceptions: &[Option<eh_artiq::Exception>],
stack_pointers: &[eh_artiq::StackPointerBacktrace],
backtrace: &[(usize, usize)],
) -> Result<(), Error> {
) -> Result<(), W::Error> {
/* header */
writer.write_bytes::<NativeEndian>(&[0x5a, 0x5a, 0x5a, 0x5a, /*Reply::KernelException*/ 9])?;
writer.write_u32::<NativeEndian>(exceptions.len() as u32)?;