M-Labs/artiq-zynq
10
1
Fork 19
Code Issues 12 Pull Requests Releases Wiki Activity

sram: rewrote read fsm for sram

Browse Source
This commit is contained in:
mwojcik 2021-08-13 14:14:43 +02:00
parent 39509f01d6
commit bfe0c34f57
1 changed files with 17 additions and 29 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

46
src/gateware/aux_controller.py
View File

@ -36,8 +36,6 @@ class SRAM(Module):
# probably will get removed # probably will get removed
self.addr_base = CSRStorage(32) self.addr_base = CSRStorage(32)
self.trig_count = CSRStatus(32)
self.write_count = CSRStatus(32)
self.trigger_stb = Signal() self.trigger_stb = Signal()
@ -47,11 +45,8 @@ class SRAM(Module):
# data # data
# #
# Cycle: # Cycle:
# trigger_stb pulsed at start
# Then out_burst_len words are strobed out of dout # Then out_burst_len words are strobed out of dout
# Then, when din_ready is high, in_burst_len words are strobed in to din # Then, when din_ready is high, in_burst_len words are strobed in to din
self.dout_stb = Signal() # there's no strobe signal for SRAM
self.din_stb = Signal()
self.dout_index = Signal(bus_addr_width) # is this legal? self.dout_index = Signal(bus_addr_width) # is this legal?
self.din_index = Signal(bus_addr_width) self.din_index = Signal(bus_addr_width)
self.din_ready = Signal() self.din_ready = Signal()
@ -65,8 +60,8 @@ class SRAM(Module):
### Read ### Read
self.comb += [ self.comb += [
ar.addr.eq(port.adr), # shouldn't it be the other way around? port.adr.eq(ar.addr),
port.dat_r.eq(r.data), r.data.eq(port.dat_r),
r.ready.eq(1), r.ready.eq(1),
ar.burst.eq(axi.Burst.incr.value), ar.burst.eq(axi.Burst.incr.value),
ar.len.eq(OUT_BURST_LEN-1), # Number of transfers in burst (0->1 transfer, 1->2 transfers...) ar.len.eq(OUT_BURST_LEN-1), # Number of transfers in burst (0->1 transfer, 1->2 transfers...)
@ -77,45 +72,41 @@ class SRAM(Module):
# read control # read control
self.submodules.read_fsm = read_fsm = FSM(reset_state="IDLE") self.submodules.read_fsm = read_fsm = FSM(reset_state="IDLE")
read_fsm.act("IDLE", read_fsm.act("IDLE",
If(self.trigger_stb, If(ar.valid,
ar.valid.eq(1), ar.ready.eq(1),
If(ar.ready, NextState("READ_START"),
NextState("READ")
).Else(
NextState("READ_START")
)
) )
) )
read_fsm.act("READ_START", read_fsm.act("READ_START",
ar.valid.eq(1), If(r.valid,
If(ar.ready, r.ready.eq(1),
NextState("READ"), r.data.eq(port.dat_r), # that should be always updated, right?
) NextState("READ"))
) )
read_fsm.act("READ", read_fsm.act("READ",
ar.valid.eq(0), If(r.last & r.valid, # that's a smart way of skipping "LAST" state
If(r.last & r.valid, r.data.eq(port.dat_r),
NextState("IDLE") NextState("IDLE")
) )
) )
self.sync += [ self.sync += [
If(read_fsm.ongoing("IDLE"), If(read_fsm.ongoing("IDLE"),
self.dout_index.eq(0) self.dout_index.eq(0),
r.ready.eq(0), # shall it be reset too on IDLE?
ar.ready.eq(0)
).Else(If(r.valid & read_fsm.ongoing("READ"), ).Else(If(r.valid & read_fsm.ongoing("READ"),
self.dout_index.eq(self.dout_index+1), self.dout_index.eq(self.dout_index+1),
port.adr.eq(port.adr + self.dout_index) # update address in the port port.adr.eq(port.adr + self.dout_index), # update address in the port
If(self.dout_index==ar.len, r.last.eq(1)) # and update last
) )
) )
] ]
# possibly unnecessary too
self.comb += self.dout_stb.eq(r.valid & r.ready)
### Write ### Write
self.comb += [ self.comb += [
w.data.eq(port.dat_w), w.data.eq(port.dat_w),
aw.addr.eq(port.addr), # shouldn't it be the other way around? port.addr.eq(aw.addr),
w.strb.eq(0xff), w.strb.eq(0xff),
aw.burst.eq(axi.Burst.incr.value), aw.burst.eq(axi.Burst.incr.value),
aw.len.eq(IN_BURST_LEN-1), # Number of transfers in burst minus 1 aw.len.eq(IN_BURST_LEN-1), # Number of transfers in burst minus 1
@ -172,9 +163,6 @@ class SRAM(Module):
If(self.din_index==aw.len, w.last.eq(1)) If(self.din_index==aw.len, w.last.eq(1))
] ]
# check if necessary
self.comb += self.din_stb.eq(w.valid & w.ready)
# # generate write enable signal # # generate write enable signal
# if not read_only: # if not read_only: