From bb5af4f156feb45f240a43baaa93cd4c61a5f2c3 Mon Sep 17 00:00:00 2001 From: mwojcik Date: Thu, 23 Sep 2021 14:22:30 +0200 Subject: [PATCH] gateware: fixing up master classes --- src/gateware/kasli_soc.py | 8 +++---- src/gateware/zc706.py | 45 +++++++++++++++++++++++++++++++++++---- 2 files changed, 45 insertions(+), 8 deletions(-) diff --git a/src/gateware/kasli_soc.py b/src/gateware/kasli_soc.py index 505611f..1e02c6b 100755 --- a/src/gateware/kasli_soc.py +++ b/src/gateware/kasli_soc.py @@ -211,7 +211,6 @@ class GenericMaster(SoCCore): def __init__(self, description, acpki=False): sys_clk_freq = 125e6 - rtio_clk_freq = 125e6 # should this be pulled from description? rtio freq isnt set self.acpki = acpki self.rustc_cfg = dict() @@ -284,10 +283,11 @@ class GenericMaster(SoCCore): coreaux = cdr(aux_controller.DRTIOAuxControllerBare(core.link_layer)) setattr(self.submodules, coreaux_name, coreaux) self.csr_devices.append(coreaux_name) - - memory_address, size = self.axi2csr.add_memory(coreaux.transmitter.mem, read_only=False) + + mem_size = coreaux.get_mem_size() + memory_address, size = self.axi2csr.add_port(coreaux.get_tx_port(), mem_size) # rcv in upper half of the memory, thus added second - self.axi2csr.add_memory(coreaux.receiver.mem, read_only=False) + self.axi2csr.add_prot(coreaux.get_rx_port(), mem_size) self.add_memory_region(memory_name, self.mem_map["csr"] + memory_address, size * 2) self.rustc_cfg["has_drtio"] = None self.rustc_cfg["has_drtio_routing"] = None diff --git a/src/gateware/zc706.py b/src/gateware/zc706.py index 5a59750..ca56062 100755 --- a/src/gateware/zc706.py +++ b/src/gateware/zc706.py @@ -246,12 +246,14 @@ class _MasterBase(SoCCore): drtio_cri.append(core.cri) self.csr_devices.append(core_name) - coreaux = cdr(aux_controller.DRTIOAuxControllerAxi(core.link_layer)) + coreaux = cdr(aux_controller.DRTIOAuxControllerBare(core.link_layer)) setattr(self.submodules, coreaux_name, coreaux) self.csr_devices.append(coreaux_name) - memory_address = self.mem_map["drtioaux"] + 0x800*i - self.register_mem(memory_name, memory_address, 0x800, coreaux.bus) + mem_size = coreaux.get_mem_size() + memory_address = self.axi2csr.register_port(coreaux.get_tx_port(), mem_size) + self.axi2csr.register_port(coreaux.get_rx_port(), mem_size) + self.add_memory_region(memory_name, self.mem_map["csr"] + memory_address, mem_size * 2) self.config["has_drtio"] = None self.config["has_drtio_routing"] = None self.add_csr_group("drtio", drtio_csr_group) @@ -284,7 +286,42 @@ class _MasterBase(SoCCore): platform.add_false_path_constraints( self.ps7.cd_sys.clk, gtx0.txoutclk, gtx.rxoutclk) - self.rtio_crg = RTIOCRG(self.platform, self.drtio_transceiver.rtio_clk_freq) + def add_rtio(self, rtio_channels): + self.submodules.rtio_tsc = rtio.TSC("async", glbl_fine_ts_width=3) + self.submodules.rtio_core = rtio.Core(self.rtio_tsc, rtio_channels) + self.csr_devices.append("rtio_core") + + if self.acpki: + self.rustc_cfg["ki_impl"] = "acp" + self.submodules.rtio = acpki.KernelInitiator(self.rtio_tsc, + bus=self.ps7.s_axi_acp, + user=self.ps7.s_axi_acp_user, + evento=self.ps7.event.o) + self.csr_devices.append("rtio") + else: + self.rustc_cfg["ki_impl"] = "csr" + self.submodules.rtio = rtio.KernelInitiator(self.rtio_tsc, now64=True) + self.csr_devices.append("rtio") + + self.submodules.rtio_dma = dma.DMA(self.ps7.s_axi_hp0) + self.csr_devices.append("rtio_dma") + + self.submodules.local_io = SyncRTIO(self.rtio_tsc, rtio_channels) + self.submodules.cri_con = rtio.CRIInterconnectShared( + [self.drtiosat.cri], + [self.local_io.cri] + self.drtio_cri, + mode="sync", enable_routing=True) + self.csr_devices.append("cri_con") + + self.submodules.rtio_moninj = rtio.MonInj(rtio_channels) + self.csr_devices.append("rtio_moninj") + + self.submodules.rtio_analyzer = analyzer.Analyzer(self.rtio_tsc, self.rtio_core.cri, + self.ps7.s_axi_hp1) + self.csr_devices.append("rtio_analyzer") + + self.submodules.routing_table = rtio.RoutingTableAccess(self.cri_con) + self.csr_devices.append("routing_table") class _SatelliteBase(SoCCore):