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sram: fixed wrong assumptions on some signals

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This commit is contained in:
mwojcik 2021-08-13 14:58:18 +02:00
parent bfe0c34f57
commit b6dd5bea68
1 changed files with 6 additions and 7 deletions
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13
src/gateware/aux_controller.py
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@ -37,8 +37,6 @@ class SRAM(Module):
# probably will get removed # probably will get removed
self.addr_base = CSRStorage(32) self.addr_base = CSRStorage(32)
self.trigger_stb = Signal()
# Dout : Data received from CPU, output by SRAM <- port.dat_r # Dout : Data received from CPU, output by SRAM <- port.dat_r
# Din : Data driven into SRAM, written into CPU <- port.dat_w # Din : Data driven into SRAM, written into CPU <- port.dat_w
# When stb assert, index shows word being read/written, dout/din holds <- will be removed # When stb assert, index shows word being read/written, dout/din holds <- will be removed
@ -78,14 +76,15 @@ class SRAM(Module):
) )
) )
read_fsm.act("READ_START", read_fsm.act("READ_START",
If(r.valid, r.data.eq(port.dat_r),
r.ready.eq(1), r.valid.eq(1),
If(r.ready,
r.data.eq(port.dat_r), # that should be always updated, right? r.data.eq(port.dat_r), # that should be always updated, right?
NextState("READ")) NextState("READ"))
) )
read_fsm.act("READ", read_fsm.act("READ",
If(r.last & r.valid, # that's a smart way of skipping "LAST" state r.data.eq(port.dat_r),
r.data.eq(port.dat_r), If(r.last & r.ready, # that's a smart way of skipping "LAST" state
NextState("IDLE") NextState("IDLE")
) )
) )
@ -95,7 +94,7 @@ class SRAM(Module):
self.dout_index.eq(0), self.dout_index.eq(0),
r.ready.eq(0), # shall it be reset too on IDLE? r.ready.eq(0), # shall it be reset too on IDLE?
ar.ready.eq(0) ar.ready.eq(0)
).Else(If(r.valid & read_fsm.ongoing("READ"), ).Else(If(r.ready & read_fsm.ongoing("READ"),
self.dout_index.eq(self.dout_index+1), self.dout_index.eq(self.dout_index+1),
port.adr.eq(port.adr + self.dout_index), # update address in the port port.adr.eq(port.adr + self.dout_index), # update address in the port
If(self.dout_index==ar.len, r.last.eq(1)) # and update last If(self.dout_index==ar.len, r.last.eq(1)) # and update last