M-Labs/artiq-zynq
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rustc_cfg is case sensitive. Si5324 was not achnowledged.

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This commit is contained in:
mwojcik 2021-09-03 14:58:17 +02:00
parent 0c259d9833
commit b678408105
5 changed files with 22 additions and 18 deletions
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6
src/gateware/zc706.py
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@ -395,7 +395,7 @@ class Satellite(SoCCore):
platform = self.platform
# SFP
self.comb += platform.request("sfp_tx_disable_n").eq(1)
self.comb += platform.request("sfp_tx_disable_n").eq(0)
data_pads = [
platform.request("sfp")
]
@ -442,7 +442,7 @@ class Satellite(SoCCore):
self.add_csr_group("drtioaux", drtioaux_csr_group)
self.add_memory_group("drtioaux_mem", drtioaux_memory_group)
self.rustc_cfg["RTIO_FREQUENCY"] = str(self.drtio_transceiver.rtio_clk_freq/1e6)
self.rustc_cfg["rtio_frequency"] = str(self.drtio_transceiver.rtio_clk_freq/1e6)
# Si5324 Phaser
self.submodules.siphaser = SiPhaser7Series(
@ -455,7 +455,7 @@ class Satellite(SoCCore):
self.csr_devices.append("siphaser")
self.submodules.si5324_rst_n = gpio.GPIOOut(platform.request("si5324").rst_n)
self.csr_devices.append("si5324_rst_n")
self.rustc_cfg["HAS_SI5324"] = None
self.rustc_cfg["has_si5324"] = None
rtio_clk_period = 1e9/self.drtio_transceiver.rtio_clk_freq
# Constrain TX & RX timing for the first transceiver channel

1
src/libboard_artiq/Cargo.toml
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@ -14,6 +14,7 @@ log = "0.4"
log_buffer = { version = "1.2" }
crc = { version = "1.7", default-features = false }
core_io = { version = "0.1", features = ["collections"] }
embedded-hal = "0.2"
io = { path = "../libio", features = ["byteorder"] }
libboard_zynq = { git = "https://git.m-labs.hk/M-Labs/zynq-rs.git"}

6
src/libboard_artiq/src/lib.rs
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@ -3,13 +3,15 @@
extern crate log;
extern crate crc;
extern crate embedded_hal;
extern crate core_io;
extern crate io;
extern crate libboard_zynq;
extern crate libregister;
extern crate libconfig;
extern crate libcortex_a9;
extern crate log_buffer;
extern crate io;
extern crate core_io;
// has csr; taken from runtime main
#[path = "../../../build/pl.rs"]

20
src/libboard_artiq/src/si5324.rs
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@ -10,7 +10,7 @@ type Result<T> = result::Result<T, &'static str>;
const ADDRESS: u8 = 0x68;
#[cfg(not(si5324_soft_reset))]
fn hard_reset(timer: GlobalTimer) {
fn hard_reset(timer: &mut GlobalTimer) {
unsafe { csr::si5324_rst_n::out_write(0); }
timer.delay_us(1_000);
unsafe { csr::si5324_rst_n::out_write(1); }
@ -147,7 +147,7 @@ fn ident(i2c: &mut I2c) -> Result<u16> {
}
#[cfg(si5324_soft_reset)]
fn soft_reset(i2c: &mut I2c, timer: GlobalTimer) -> Result<()> {
fn soft_reset(i2c: &mut I2c, timer: &mut GlobalTimer) -> Result<()> {
write_no_ack_value(i2c, 136, read(i2c, 136)? | 0x80)?;
timer.delay_us(10_000);
Ok(())
@ -168,7 +168,7 @@ fn locked(i2c: &mut I2c) -> Result<bool> {
Ok((read(i2c, 130)? & 0x01) == 0) // LOL_INT=0
}
fn monitor_lock(i2c: &mut I2c, timer: GlobalTimer) -> Result<()> {
fn monitor_lock(i2c: &mut I2c, timer: &mut GlobalTimer) -> Result<()> {
info!("waiting for Si5324 lock...");
let timeout = timer.get_time() + Milliseconds(20_000);
while !locked(i2c)? {
@ -181,7 +181,7 @@ fn monitor_lock(i2c: &mut I2c, timer: GlobalTimer) -> Result<()> {
Ok(())
}
fn init(i2c: &mut I2c, timer: GlobalTimer) -> Result<()> {
fn init(i2c: &mut I2c, timer: &mut GlobalTimer) -> Result<()> {
#[cfg(not(si5324_soft_reset))]
hard_reset(timer);
@ -200,7 +200,7 @@ fn init(i2c: &mut I2c, timer: GlobalTimer) -> Result<()> {
Ok(())
}
pub fn bypass(i2c: &mut I2c, input: Input, timer: GlobalTimer) -> Result<()> {
pub fn bypass(i2c: &mut I2c, input: Input, timer: &mut GlobalTimer) -> Result<()> {
let cksel_reg = match input {
Input::Ckin1 => 0b00,
Input::Ckin2 => 0b01,
@ -214,7 +214,7 @@ pub fn bypass(i2c: &mut I2c, input: Input, timer: GlobalTimer) -> Result<()> {
Ok(())
}
pub fn setup(i2c: &mut I2c, settings: &FrequencySettings, input: Input, timer: GlobalTimer) -> Result<()> {
pub fn setup(i2c: &mut I2c, settings: &FrequencySettings, input: Input, timer: &mut GlobalTimer) -> Result<()> {
let s = map_frequency_settings(settings)?;
let cksel_reg = match input {
Input::Ckin1 => 0b00,
@ -260,7 +260,7 @@ pub fn setup(i2c: &mut I2c, settings: &FrequencySettings, input: Input, timer: G
Ok(())
}
pub fn select_input(i2c: &mut I2c, input: Input, timer: GlobalTimer) -> Result<()> {
pub fn select_input(i2c: &mut I2c, input: Input, timer: &mut GlobalTimer) -> Result<()> {
let cksel_reg = match input {
Input::Ckin1 => 0b00,
Input::Ckin2 => 0b01,
@ -278,7 +278,7 @@ pub mod siphaser {
use super::*;
use pl::csr;
pub fn select_recovered_clock(i2c: &mut I2c, rc: bool, timer: GlobalTimer) -> Result<()> {
pub fn select_recovered_clock(i2c: &mut I2c, rc: bool, timer: &mut GlobalTimer) -> Result<()> {
write(i2c, 3, (read(3)? & 0xdf) | (1 << 5))?; // DHOLD=1
unsafe {
csr::siphaser::switch_clocks_write(if rc { 1 } else { 0 });
@ -307,7 +307,7 @@ pub mod siphaser {
}
}
fn find_edge(target: bool, timer: GlobalTimer) -> Result<u32> {
fn find_edge(target: bool, timer: &mut GlobalTimer) -> Result<u32> {
let mut nshifts = 0;
let mut previous = has_error(timer);
@ -325,7 +325,7 @@ pub mod siphaser {
}
}
pub fn calibrate_skew(timer: GlobalTimer) -> Result<()> {
pub fn calibrate_skew(timer: &mut GlobalTimer) -> Result<()> {
let jitter_margin = 32;
let lead = find_edge(false, timer)?;
for _ in 0..jitter_margin {

7
src/satman/src/main.rs
View File

@ -419,6 +419,7 @@ const SI5324_SETTINGS: si5324::FrequencySettings
crystal_ref: true
};
// rtio frequencies other than 125 MHz won't be supported?
#[cfg(all(has_si5324, rtio_frequency = "125.0"))]
const SI5324_SETTINGS: si5324::FrequencySettings
= si5324::FrequencySettings {
@ -460,7 +461,7 @@ pub extern fn main_core0() -> i32 {
//this part was commented in runtime
#[cfg(has_si5324)]
si5324::setup(&SI5324_SETTINGS, si5324::Input::Ckin1).expect("cannot initialize Si5324");
si5324::setup(&mut i2c, &SI5324_SETTINGS, si5324::Input::Ckin1, &mut timer).expect("cannot initialize Si5324");
unsafe {
csr::drtio_transceiver::stable_clkin_write(1);
@ -495,7 +496,7 @@ pub extern fn main_core0() -> i32 {
}
info!("uplink is up, switching to recovered clock");
#[cfg(has_si5324)]
#[cfg(has_siphaser)]
{
si5324::siphaser::select_recovered_clock(true).expect("failed to switch clocks");
si5324::siphaser::calibrate_skew().expect("failed to calibrate skew");
@ -530,7 +531,7 @@ pub extern fn main_core0() -> i32 {
drtiosat_reset(true);
drtiosat_tsc_loaded();
info!("uplink is down, switching to local oscillator clock");
#[cfg(has_si5324)]
#[cfg(has_siphaser)]
si5324::siphaser::select_recovered_clock(false).expect("failed to switch clocks");
}
}