zc706: added memory iface generator
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1358c8bfe9
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@ -530,6 +530,11 @@ def write_csr_file(soc, filename):
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f.write(cpu_interface.get_csr_rust(
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f.write(cpu_interface.get_csr_rust(
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soc.get_csr_regions(), soc.get_csr_groups(), soc.get_constants()))
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soc.get_csr_regions(), soc.get_csr_groups(), soc.get_constants()))
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def write_mem_file(soc, filename):
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with open(filename, "w") as f:
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f.write(cpu_interface.get_mem_rust(
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soc.get_memory_regions(), soc.get_memory_groups(), None))
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def write_rustc_cfg_file(soc, filename):
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def write_rustc_cfg_file(soc, filename):
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with open(filename, "w") as f:
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with open(filename, "w") as f:
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@ -545,6 +550,8 @@ def main():
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description="ARTIQ port to the ZC706 Zynq development kit")
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description="ARTIQ port to the ZC706 Zynq development kit")
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parser.add_argument("-r", default=None,
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parser.add_argument("-r", default=None,
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help="build Rust interface into the specified file")
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help="build Rust interface into the specified file")
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parser.add_argument("-m", default=None,
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help="build Rust memory interface into the specified file")
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parser.add_argument("-c", default=None,
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parser.add_argument("-c", default=None,
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help="build Rust compiler configuration into the specified file")
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help="build Rust compiler configuration into the specified file")
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parser.add_argument("-g", default=None,
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parser.add_argument("-g", default=None,
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@ -567,8 +574,12 @@ def main():
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soc = cls(acpki=acpki)
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soc = cls(acpki=acpki)
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soc.finalize()
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soc.finalize()
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print(soc.get_memory_regions())
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if args.r is not None:
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if args.r is not None:
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write_csr_file(soc, args.r)
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write_csr_file(soc, args.r)
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if args.m is not None:
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write_mem_file(soc, args.m)
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if args.c is not None:
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if args.c is not None:
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write_rustc_cfg_file(soc, args.c)
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write_rustc_cfg_file(soc, args.c)
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if args.g is not None:
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if args.g is not None:
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