From b11f689e2dca7e332b71ff2ef6feba86d2f0617c Mon Sep 17 00:00:00 2001 From: mwojcik Date: Thu, 7 Oct 2021 11:44:43 +0200 Subject: [PATCH] zc706: added user_sma_mgt, repeaters for sat --- src/gateware/zc706.py | 20 +++++++++++++++----- 1 file changed, 15 insertions(+), 5 deletions(-) diff --git a/src/gateware/zc706.py b/src/gateware/zc706.py index 95441fe..0f71b20 100755 --- a/src/gateware/zc706.py +++ b/src/gateware/zc706.py @@ -171,7 +171,8 @@ class _MasterBase(SoCCore): self.comb += platform.request("sfp_tx_disable_n").eq(1) data_pads = [ - platform.request("sfp") + platform.request("sfp"), + platform.request("user_sma_mgt") ] # 1000BASE_BX10 Ethernet compatible, 125MHz RTIO clock @@ -302,7 +303,8 @@ class _SatelliteBase(SoCCore): # SFP self.comb += platform.request("sfp_tx_disable_n").eq(0) data_pads = [ - platform.request("sfp") + platform.request("sfp"), + platform.request("user_sma_mgt") ] self.submodules.rtio_tsc = rtio.TSC("sync", glbl_fine_ts_width=3) @@ -316,6 +318,7 @@ class _SatelliteBase(SoCCore): drtioaux_csr_group = [] drtioaux_memory_group = [] + drtiorep_csr_group = [] self.drtio_cri = [] for i in range(len(self.drtio_transceiver.channels)): coreaux_name = "drtioaux" + str(i) @@ -332,8 +335,15 @@ class _SatelliteBase(SoCCore): self.rtio_tsc, self.drtio_transceiver.channels[0], self.rx_synchronizer)) self.submodules.drtiosat = core self.csr_devices.append("drtiosat") - # Repeaters - there would be for i != 0 - however zc706 only has one SFP - # and no other means to connect to + # Repeaters + else: + corerep_name = "drtiorep" + str(i-1) + drtiorep_csr_group.append(corerep_name) + core = cdr(DRTIORepeater( + self.rtio_tsc, self.drtio_transceiver.channels[i])) + setattr(self.submodules, corerep_name, core) + self.drtio_cri.append(core.cri) + self.csr_devices.append(corerep_name) coreaux = cdr(drtio_aux_controller.DRTIOAuxControllerBare(core.link_layer)) setattr(self.submodules, coreaux_name, coreaux) @@ -349,7 +359,7 @@ class _SatelliteBase(SoCCore): # manually, because software refers to rx/tx by halves of entire memory block, not names self.add_memory_region(memory_name, self.mem_map["csr"] + memory_address, mem_size * 2) self.rustc_cfg["has_drtio"] = None - # no repeaters - it does not have drtio routing support + self.rustc_cfg["has_drtio_routing"] = None self.add_csr_group("drtioaux", drtioaux_csr_group) self.add_memory_group("drtioaux_mem", drtioaux_memory_group)