From ae7ca22db96426c5edba6c152520131a2ea6579d Mon Sep 17 00:00:00 2001 From: Sebastien Bourdeauducq Date: Thu, 16 Jul 2020 17:26:25 +0800 Subject: [PATCH] dma: fix endianness issues --- src/gateware/analyzer.py | 11 ++--------- src/gateware/dma.py | 4 +++- src/gateware/endianness.py | 21 +++++++++++++++++++++ src/gateware/test_dma.py | 2 ++ 4 files changed, 28 insertions(+), 10 deletions(-) create mode 100644 src/gateware/endianness.py diff --git a/src/gateware/analyzer.py b/src/gateware/analyzer.py index 45030fe..1247f84 100644 --- a/src/gateware/analyzer.py +++ b/src/gateware/analyzer.py @@ -6,14 +6,7 @@ from migen_axi.interconnect import axi from artiq.gateware.rtio.analyzer import message_len, MessageEncoder - -def convert_endianness(signal): - assert len(signal) % 8 == 0 - nbytes = len(signal)//8 - signal_bytes = [] - for i in range(nbytes): - signal_bytes.append(signal[8*i:8*(i+1)]) - return Cat(*reversed(signal_bytes)) +import endianness class AXIDMAWriter(Module, AutoCSR): @@ -64,7 +57,7 @@ class AXIDMAWriter(Module, AutoCSR): membus.w.id.eq(0), membus.w.valid.eq(self.sink.stb), self.sink.ack.eq(membus.w.ready), - membus.w.data.eq(convert_endianness(self.sink.data)), + membus.w.data.eq(endianness.convert_signal(self.sink.data)), membus.w.strb.eq(2**(dw//8)-1), ] beat_count = Signal(max=burst_length) diff --git a/src/gateware/dma.py b/src/gateware/dma.py index 2d8fd72..ef0555e 100644 --- a/src/gateware/dma.py +++ b/src/gateware/dma.py @@ -6,6 +6,8 @@ from migen_axi.interconnect import axi from artiq.gateware.rtio.dma import RawSlicer, RecordConverter, RecordSlicer, TimeOffset, CRIMaster +import endianness + AXI_BURST_LEN = 16 @@ -50,7 +52,7 @@ class AXIReader(Module): self.comb += [ self.source.stb.eq(membus.r.valid), membus.r.ready.eq(self.source.ack), - self.source.data.eq(membus.r.data), + self.source.data.eq(endianness.convert_signal(membus.r.data)), # Note that when eop_pending=1, no new transactions are made and inflight_cnt is no longer incremented self.source.eop.eq(eop_pending & membus.r.last & (inflight_cnt == 1)) ] diff --git a/src/gateware/endianness.py b/src/gateware/endianness.py new file mode 100644 index 0000000..ff5450e --- /dev/null +++ b/src/gateware/endianness.py @@ -0,0 +1,21 @@ +from migen import * + + +def convert_signal(signal): + assert len(signal) % 8 == 0 + nbytes = len(signal)//8 + signal_bytes = [] + for i in range(nbytes): + signal_bytes.append(signal[8*i:8*(i+1)]) + return Cat(*reversed(signal_bytes)) + + +def convert_value(value, size): + assert size % 8 == 0 + nbytes = size//8 + result = 0 + for i in range(nbytes): + result <<= 8 + result |= value & 0xff + value >>= 8 + return result diff --git a/src/gateware/test_dma.py b/src/gateware/test_dma.py index 1b972c3..0381664 100644 --- a/src/gateware/test_dma.py +++ b/src/gateware/test_dma.py @@ -10,6 +10,7 @@ from artiq.gateware import rtio from artiq.gateware.rtio import cri from artiq.gateware.rtio.phy import ttl_simple +import endianness import dma @@ -47,6 +48,7 @@ class AXIMemorySim: data = self.data[addr] else: data = 0 + data = endianness.convert_value(data, len(self.bus.r.data)) yield from self.bus.write_r(request.id, data, last=i == request_len-1) else: yield