use external clock for bootstrap instead of fclk0

src/gateware/kasli_soc.py

@@ -61,6 +61,23 @@ class SMAClkinForward(Module):
         ]
 
 
+class GTP125BootstrapClock(Module):
+    def __init__(self, platform):
+        self.clock_domains.cd_bootstrap = ClockDomain(reset_less=True)
+        self.cd_bootstrap.clk.attr.add("keep")
+
+        bootstrap_125 = platform.request("clk125_gtp")
+        bootstrap_se = Signal()
+        platform.add_period_constraint(bootstrap_125.p, 8.0)
+        self.specials += [
+            Instance("IBUFDS_GTE2",
+                p_CLKSWING_CFG="0b11",
+                i_CEB=0,
+                i_I=bootstrap_125.p, i_IB=bootstrap_125.n, o_O=bootstrap_se),
+            Instance("BUFG", i_I=bootstrap_se, o_O=self.cd_bootstrap.clk)
+        ]
+
+
 class GenericStandalone(SoCCore):
     def __init__(self, description, acpki=False):
         self.acpki = acpki
@@ -75,9 +92,6 @@ class GenericStandalone(SoCCore):
             ident = "acpki_" + ident
         SoCCore.__init__(self, platform=platform, csr_data_width=32, ident=ident, ps_cd_sys=False)
 
-        platform.add_platform_command("create_clock -name clk_fpga_0 -period 8 [get_pins \"PS7/FCLKCLK[0]\"]")
-        platform.add_platform_command("set_input_jitter clk_fpga_0 0.24")
-
         self.submodules += SMAClkinForward(self.platform)
 
         self.rustc_cfg["has_si5324"] = None
@@ -86,15 +100,17 @@ class GenericStandalone(SoCCore):
         clk_synth = platform.request("cdr_clk_clean_fabric")
         clk_synth_se = Signal()
         platform.add_period_constraint(clk_synth.p, 8.0)
-        self.specials += [
+
-            Instance("IBUFGDS",
+        self.specials += Instance("IBUFGDS",
                 p_DIFF_TERM="TRUE", p_IBUF_LOW_PWR="FALSE",
-                i_I=clk_synth.p, i_IB=clk_synth.n, o_O=clk_synth_se),
+                i_I=clk_synth.p, i_IB=clk_synth.n, o_O=clk_synth_se)
-        ]
         fix_serdes_timing_path(platform)
+        self.submodules.bootstrap = GTP125BootstrapClock(self.platform)
 
         self.crg = self.ps7 # HACK for eem_7series to find the clock
         self.submodules.sys_crg = zynq_clocking.SYSCRG(self.platform, self.ps7, clk_synth_se)
+        platform.add_false_path_constraints(
+            self.bootstrap.cd_bootstrap.clk, self.sys_crg.cd_sys.clk)
         self.csr_devices.append("sys_crg")
         # another hack since ps7 itself does not have cd_sys anymore
         self.crg.cd_sys = self.sys_crg.cd_sys
@@ -168,9 +184,6 @@ class GenericMaster(SoCCore):
             ident = "acpki_" + ident
         SoCCore.__init__(self, platform=platform, csr_data_width=32, ident=ident, ps_cd_sys=False)
 
-        platform.add_platform_command("create_clock -name clk_fpga_0 -period 8 [get_pins \"PS7/FCLKCLK[0]\"]")
-        platform.add_platform_command("set_input_jitter clk_fpga_0 0.24")
-
         self.submodules += SMAClkinForward(self.platform)
 
         data_pads = [platform.request("sfp", i) for i in range(4)]
@@ -184,6 +197,8 @@ class GenericMaster(SoCCore):
         txout_buf = Signal()
         gtx0 = self.drtio_transceiver.gtxs[0]
         self.specials += Instance("BUFG", i_I=gtx0.txoutclk, o_O=txout_buf)
+
+        self.submodules.bootstrap = GTP125BootstrapClock(self.platform)
         self.submodules.sys_crg = zynq_clocking.SYSCRG(
             self.platform,
             self.ps7,
@@ -193,6 +208,8 @@ class GenericMaster(SoCCore):
         self.crg = self.ps7 # HACK for eem_7series to find the clock
         # another hack since ps7 itself does not have cd_sys anymore
         self.crg.cd_sys = self.sys_crg.cd_sys
+        platform.add_false_path_constraints(
+            self.bootstrap.cd_bootstrap.clk, self.sys_crg.cd_sys.clk)
         fix_serdes_timing_path(platform)
 
         self.rustc_cfg["has_si5324"] = None
@@ -302,9 +319,6 @@ class GenericSatellite(SoCCore):
             ident = "acpki_" + ident
         SoCCore.__init__(self, platform=platform, csr_data_width=32, ident=ident, ps_cd_sys=False)
 
-        platform.add_platform_command("create_clock -name clk_fpga_0 -period 8 [get_pins \"PS7/FCLKCLK[0]\"]")
-        platform.add_platform_command("set_input_jitter clk_fpga_0 0.24")
-
         self.crg = self.ps7 # HACK for eem_7series to find the clock
 
         data_pads = [platform.request("sfp", i) for i in range(4)]
@@ -318,11 +332,15 @@ class GenericSatellite(SoCCore):
         txout_buf = Signal()
         gtx0 = self.drtio_transceiver.gtxs[0]
         self.specials += Instance("BUFG", i_I=gtx0.txoutclk, o_O=txout_buf)
+
+        self.submodules.bootstrap = GTP125BootstrapClock(self.platform)
         self.submodules.sys_crg = zynq_clocking.SYSCRG(
             self.platform, 
             self.ps7,
             txout_buf,
             clk_sw=gtx0.tx_init.done)
+        platform.add_false_path_constraints(
+            self.bootstrap.cd_bootstrap.clk, self.sys_crg.cd_sys.clk)
         self.csr_devices.append("sys_crg")
         self.crg.cd_sys = self.sys_crg.cd_sys
 

src/gateware/zc706.py

@@ -41,6 +41,36 @@ class SMAClkinForward(Module):
         ]
 
 
+class CLK200BootstrapClock(Module):
+    def __init__(self, platform):
+        self.clock_domains.cd_bootstrap = ClockDomain(reset_less=True)
+        self.cd_bootstrap.clk.attr.add("keep")
+
+
+        clk200 = platform.request("clk200")
+        clk200_se = Signal()
+
+        pll_fb = Signal()
+        pll_clk125 = Signal()
+        self.specials += [
+            Instance("IBUFDS",
+                i_I=clk200.p, i_IB=clk200.n, o_O=clk200_se),
+            Instance("PLLE2_BASE",
+                p_CLKIN1_PERIOD=5.0,
+                i_CLKIN1=clk200_se,
+                i_CLKFBIN=pll_fb,
+                o_CLKFBOUT=pll_fb,
+
+                # VCO @ 1GHz
+                p_CLKFBOUT_MULT=5, p_DIVCLK_DIVIDE=1,
+
+                # 125MHz for bootstrap
+                p_CLKOUT1_DIVIDE=8, p_CLKOUT1_PHASE=0.0, o_CLKOUT1=pll_clk125,
+            ),
+            Instance("BUFG", i_I=pll_clk125, o_O=self.cd_bootstrap.clk)
+        ]
+
+
 # The NIST backplanes require setting VADJ to 3.3V by reprogramming the power supply.
 # This also changes the I/O standard for some on-board LEDs.
 leds_fmc33 = [
@@ -129,8 +159,11 @@ class ZC706(SoCCore):
         self.rustc_cfg["has_si5324"] = None
         self.rustc_cfg["si5324_as_synthesizer"] = None
         self.rustc_cfg["si5324_soft_reset"] = None
-
+        
+        self.submodules.bootstrap = CLK200BootstrapClock(platform)
         self.submodules.sys_crg = zynq_clocking.SYSCRG(self.platform, self.ps7, cdr_clk_buf)
+        platform.add_false_path_constraints(
+            self.bootstrap.cd_bootstrap.clk, self.sys_crg.cd_sys.clk)
         self.csr_devices.append("sys_crg")
 
     def add_rtio(self, rtio_channels):
@@ -201,11 +234,14 @@ class _MasterBase(SoCCore):
         txout_buf = Signal()
         gtx0 = self.drtio_transceiver.gtxs[0]
         self.specials += Instance("BUFG", i_I=gtx0.txoutclk, o_O=txout_buf)
+        self.submodules.bootstrap = CLK200BootstrapClock(platform)
         self.submodules.sys_crg = zynq_clocking.SYSCRG(
             self.platform, 
             self.ps7, 
             txout_buf,
             clk_sw=gtx0.tx_init.done)
+        platform.add_false_path_constraints(
+            self.bootstrap.cd_bootstrap.clk, self.sys_crg.cd_sys.clk)
         self.csr_devices.append("sys_crg")
 
         drtio_csr_group = []
@@ -337,11 +373,14 @@ class _SatelliteBase(SoCCore):
             "BUFG", 
             i_I=gtx0.txoutclk, 
             o_O=txout_buf)
+        self.submodules.bootstrap = CLK200BootstrapClock(platform)
         self.submodules.sys_crg = zynq_clocking.SYSCRG(
             self.platform, 
             self.ps7, 
             txout_buf,
             clk_sw=gtx0.tx_init.done)
+        platform.add_false_path_constraints(
+            self.bootstrap.cd_bootstrap.clk, self.sys_crg.cd_sys.clk)
         self.csr_devices.append("sys_crg")
 
         drtioaux_csr_group = []

src/gateware/zynq_clocking.py

@@ -65,15 +65,18 @@ class ClockSwitchFSM(Module):
 
 
 class SYSCRG(Module, AutoCSR):
-    def __init__(self, platform, ps7, main_clk, clk_sw=None):
+    def __init__(self, platform, ps7, main_clk, clk_sw=None, freq=125e6):
-        self.clock_domains.cd_bootstrap = ClockDomain(reset_less=True)
+        # assumes bootstrap clock is same freq as main and sys output
         self.clock_domains.cd_sys = ClockDomain()
         self.clock_domains.cd_sys4x = ClockDomain(reset_less=True)
 
         self.current_clock = CSRStatus()
 
         self.cd_sys.clk.attr.add("keep")
-        self.cd_bootstrap.clk.attr.add("keep")
+
+        bootstrap_clk = ClockSignal("bootstrap")
+
+        period = 1e9/freq
 
         pll_locked = Signal()
         pll_sys = Signal()
@@ -88,17 +91,14 @@ class SYSCRG(Module, AutoCSR):
             self.comb += self.clk_sw_fsm.i_clk_sw.eq(self.clock_switch.storage)
         else:
             self.comb += self.clk_sw_fsm.i_clk_sw.eq(clk_sw)
-    
-        platform.add_period_constraint(self.cd_bootstrap.clk, 8.0)
 
         self.specials += [
-            Instance("BUFG", i_I=ps7.fclk.clk[0], o_O=self.cd_bootstrap.clk),
             Instance("PLLE2_ADV",
                      p_STARTUP_WAIT="FALSE", o_LOCKED=pll_locked,
                      p_BANDWIDTH="HIGH",
                      p_REF_JITTER1=0.001,
-                     p_CLKIN1_PERIOD=8.0, i_CLKIN1=main_clk,
+                     p_CLKIN1_PERIOD=period, i_CLKIN1=main_clk,
-                     p_CLKIN2_PERIOD=8.0, i_CLKIN2=self.cd_bootstrap.clk,
+                     p_CLKIN2_PERIOD=period, i_CLKIN2=bootstrap_clk,
                      i_CLKINSEL=self.clk_sw_fsm.o_clk_sw,
 
                      # VCO @ 1.5GHz when using 125MHz input
@@ -106,7 +106,7 @@ class SYSCRG(Module, AutoCSR):
                      # do not use SYS before FCLK is configured from PS
                      p_CLKFBOUT_MULT=12, p_DIVCLK_DIVIDE=1,
                      i_CLKFBIN=fb_clk,
-                     i_RST=self.clk_sw_fsm.o_reset | ~ps7.fclk.reset_n[0],
+                     i_RST=self.clk_sw_fsm.o_reset,
 
                      o_CLKFBOUT=fb_clk,
 
@@ -118,8 +118,7 @@ class SYSCRG(Module, AutoCSR):
             Instance("BUFG", i_I=pll_sys, o_O=self.cd_sys.clk),
             Instance("BUFG", i_I=pll_sys4x, o_O=self.cd_sys4x.clk),
 
-            AsyncResetSynchronizer(self.cd_sys, ~ps7.fclk.reset_n[0] | ~pll_locked)
+            AsyncResetSynchronizer(self.cd_sys, ~pll_locked),
         ]
-        platform.add_false_path_constraints(self.cd_bootstrap.clk, main_clk)
 
         self.comb += self.current_clock.status.eq(self.clk_sw_fsm.o_clk_sw)

src/runtime/src/main.rs

@@ -22,7 +22,6 @@ use void::Void;
 use libconfig::Config;
 use libcortex_a9::l2c::enable_l2_cache;
 use libboard_artiq::{logger, identifier_read, init_gateware, pl};
-use embedded_hal::blocking::delay::DelayUs;
 
 const ASYNC_ERROR_COLLISION: u8 = 1 << 0;
 const ASYNC_ERROR_BUSY: u8 = 1 << 1;
@@ -110,7 +109,6 @@ pub fn main_core0() {
     info!("NAR3/Zynq7000 starting...");
 
     init_gateware();
-    timer.delay_us(500); // wait for FCLK to switch and PLL to lock
 
     ram::init_alloc_core0();
     gic::InterruptController::gic(mpcore::RegisterBlock::mpcore()).enable_interrupts();

src/runtime/src/rtio_clocking.rs

@@ -92,7 +92,7 @@ fn init_rtio(timer: &mut GlobalTimer) {
 #[cfg(has_drtio)]
 fn init_drtio(timer: &mut GlobalTimer)
 {
-    timer.delay_ms(1000); // wait for si output to really stabilize
+    timer.delay_ms(100); // wait for si output to really stabilize
     unsafe {
         pl::csr::drtio_transceiver::stable_clkin_write(1);
     }

src/satman/src/main.rs

@@ -454,6 +454,7 @@ pub extern fn main_core0() -> i32 {
     #[cfg(has_si5324)]
     si5324::setup(&mut i2c, &SI5324_SETTINGS, si5324::Input::Ckin1, &mut timer).expect("cannot initialize Si5324");
 
+    timer.delay_us(100_000);
     info!("Switching SYS clocks...");
     unsafe {
         csr::drtio_transceiver::stable_clkin_write(1);