From ada3f2e70400f9b8be519690c92b64de01128260 Mon Sep 17 00:00:00 2001 From: mwojcik Date: Mon, 29 Nov 2021 12:27:27 +0800 Subject: [PATCH] drtio: reading still needs work buffer after all --- src/gateware/zc706.py | 2 +- src/libboard_artiq/src/drtioaux.rs | 19 +++++++++++-------- src/libboard_artiq/src/drtioaux_async.rs | 12 +++++++----- 3 files changed, 19 insertions(+), 14 deletions(-) diff --git a/src/gateware/zc706.py b/src/gateware/zc706.py index aceb2e9..eb077f4 100755 --- a/src/gateware/zc706.py +++ b/src/gateware/zc706.py @@ -399,7 +399,7 @@ class _SatelliteBase(SoCCore): self.submodules.siphaser = SiPhaser7Series( si5324_clkin=platform.request("si5324_clkin"), rx_synchronizer=self.rx_synchronizer, - ultrascale=False, + ultrascale=True, rtio_clk_freq=self.drtio_transceiver.rtio_clk_freq) platform.add_false_path_constraints( self.ps7.cd_sys.clk, self.siphaser.mmcm_freerun_output) diff --git a/src/libboard_artiq/src/drtioaux.rs b/src/libboard_artiq/src/drtioaux.rs index f147a66..4971502 100644 --- a/src/libboard_artiq/src/drtioaux.rs +++ b/src/libboard_artiq/src/drtioaux.rs @@ -1,7 +1,6 @@ use crc; use core_io::{ErrorKind as IoErrorKind, Error as IoError}; -use core::slice; use io::{proto::ProtoRead, proto::ProtoWrite, Cursor}; use libboard_zynq::{timer::GlobalTimer, time::Milliseconds}; use crate::mem::mem::DRTIOAUX_MEM; @@ -58,13 +57,14 @@ pub fn has_rx_error(linkno: u8) -> bool { } } -pub fn copy_work_buffer(src: *mut u32, dst: *mut u32, len: isize) { +pub fn copy_work_buffer(src: *mut u16, dst: *mut u16, len: isize) { // AXI writes must be 4-byte aligned (drtio proto doesn't care for that), - // and AXI burst writes are not implemented yet in gateware + // and AXI burst reads/writes are not implemented yet in gateware // thus the need for a work buffer for transmitting and copying it over unsafe { - for i in 0..(len/4) { + for i in (0..(len/2)).step_by(2) { *dst.offset(i) = *src.offset(i); + *dst.offset(i+1) = *src.offset(i+1); } } } @@ -75,9 +75,12 @@ fn receive(linkno: u8, f: F) -> Result, Error> let linkidx = linkno as usize; unsafe { if (DRTIOAUX[linkidx].aux_rx_present_read)() == 1 { - let ptr = (DRTIOAUX_MEM[linkidx].base + DRTIOAUX_MEM[linkidx].size / 2) as *mut u8; + let ptr = (DRTIOAUX_MEM[linkidx].base + DRTIOAUX_MEM[linkidx].size / 2) as *mut u16; let len = (DRTIOAUX[linkidx].aux_rx_length_read)() as usize; - let result = f(slice::from_raw_parts(ptr as *mut u8, len as usize)); + // work buffer to accomodate axi burst reads + let mut buf: [u8; 1024] = [0; 1024]; + copy_work_buffer(ptr, buf.as_mut_ptr() as *mut u16, len as isize); + let result = f(&buf[0..len]); (DRTIOAUX[linkidx].aux_rx_present_write)(1); Ok(Some(result?)) } else { @@ -130,12 +133,12 @@ fn transmit(linkno: u8, f: F) -> Result<(), Error> let linkno = linkno as usize; unsafe { while (DRTIOAUX[linkno].aux_tx_read)() != 0 {} - let ptr = DRTIOAUX_MEM[linkno].base as *mut u32; + let ptr = DRTIOAUX_MEM[linkno].base as *mut u16; let len = DRTIOAUX_MEM[linkno].size / 2; // work buffer, works with unaligned mem access let mut buf: [u8; 1024] = [0; 1024]; let len = f(&mut buf[0..len])?; - copy_work_buffer(buf.as_mut_ptr() as *mut u32, ptr, len as isize); + copy_work_buffer(buf.as_mut_ptr() as *mut u16, ptr, len as isize); (DRTIOAUX[linkno].aux_tx_length_write)(len as u16); (DRTIOAUX[linkno].aux_tx_write)(1); Ok(()) diff --git a/src/libboard_artiq/src/drtioaux_async.rs b/src/libboard_artiq/src/drtioaux_async.rs index ae069bc..cab9791 100644 --- a/src/libboard_artiq/src/drtioaux_async.rs +++ b/src/libboard_artiq/src/drtioaux_async.rs @@ -1,7 +1,6 @@ use crc; use core_io::{ErrorKind as IoErrorKind, Error as IoError}; -use core::slice; use void::Void; use nb; @@ -43,9 +42,12 @@ async fn receive(linkno: u8, f: F) -> Result, Error> let linkidx = linkno as usize; unsafe { if (DRTIOAUX[linkidx].aux_rx_present_read)() == 1 { - let ptr = (DRTIOAUX_MEM[linkidx].base + DRTIOAUX_MEM[linkidx].size / 2) as *mut u8; + let ptr = (DRTIOAUX_MEM[linkidx].base + DRTIOAUX_MEM[linkidx].size / 2) as *mut u16; let len = (DRTIOAUX[linkidx].aux_rx_length_read)() as usize; - let result = f(slice::from_raw_parts(ptr as *mut u8, len as usize)); + // work buffer to accomodate axi burst reads + let mut buf: [u8; 1024] = [0; 1024]; + copy_work_buffer(ptr, buf.as_mut_ptr() as *mut u16, len as isize); + let result = f(&buf[0..len]); (DRTIOAUX[linkidx].aux_rx_present_write)(1); Ok(Some(result?)) } else { @@ -104,12 +106,12 @@ async fn transmit(linkno: u8, f: F) -> Result<(), Error> let linkno = linkno as usize; unsafe { let _ = block_async!(tx_ready(linkno)).await; - let ptr = DRTIOAUX_MEM[linkno].base as *mut u32; + let ptr = DRTIOAUX_MEM[linkno].base as *mut u16; let len = DRTIOAUX_MEM[linkno].size / 2; // work buffer, works with unaligned mem access let mut buf: [u8; 1024] = [0; 1024]; let len = f(&mut buf[0..len])?; - copy_work_buffer(buf.as_mut_ptr() as *mut u32, ptr, len as isize); + copy_work_buffer(buf.as_mut_ptr() as *mut u16, ptr, len as isize); (DRTIOAUX[linkno].aux_tx_length_write)(len as u16); (DRTIOAUX[linkno].aux_tx_write)(1); Ok(())