From ac459617a6cb3c9f40aee0affd0770b5a8377b4d Mon Sep 17 00:00:00 2001 From: mwojcik Date: Tue, 17 Jan 2023 18:22:59 +0800 Subject: [PATCH] rename clk signals, add "keep" attrs --- src/gateware/zynq_clocking.py | 15 +++++++++------ 1 file changed, 9 insertions(+), 6 deletions(-) diff --git a/src/gateware/zynq_clocking.py b/src/gateware/zynq_clocking.py index 92b9c60..12d1c99 100644 --- a/src/gateware/zynq_clocking.py +++ b/src/gateware/zynq_clocking.py @@ -68,9 +68,12 @@ class SYSCRG(Module, AutoCSR): self.clock_domains.cd_sys = ClockDomain() self.clock_domains.cd_sys4x = ClockDomain(reset_less=True) + self.cd_sys.clk.attr.add("keep") + pll_locked = Signal() - sys_clk = Signal() - sys4x_clk = Signal() + pll_sys = Signal() + pll_sys.attr.add("keep") + pll_sys4x = Signal() fb_clk = Signal() fclk_buf = Signal() @@ -96,12 +99,12 @@ class SYSCRG(Module, AutoCSR): o_CLKFBOUT=fb_clk, p_CLKOUT0_DIVIDE=3, p_CLKOUT0_PHASE=0.0, - o_CLKOUT0=sys4x_clk, + o_CLKOUT0=pll_sys4x, p_CLKOUT1_DIVIDE=12, p_CLKOUT1_PHASE=0.0, - o_CLKOUT1=sys_clk), - Instance("BUFG", i_I=sys_clk, o_O=self.cd_sys.clk), - Instance("BUFG", i_I=sys4x_clk, o_O=self.cd_sys4x.clk), + o_CLKOUT1=pll_sys), + Instance("BUFG", i_I=pll_sys, o_O=self.cd_sys.clk), + Instance("BUFG", i_I=pll_sys4x, o_O=self.cd_sys4x.clk), AsyncResetSynchronizer(self.cd_sys, ~pll_locked | ~ps7.fclk.reset_n[0]), ]