kasli_soc: support clock switch on drtio configs
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dba8194f09
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@ -154,8 +154,7 @@ class GenericStandalone(SoCCore):
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class GenericMaster(SoCCore):
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def __init__(self, description, acpki=False):
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sys_clk_freq = 125e6
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rtio_clk_freq = description["rtio_frequency"]
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clk_freq = description["rtio_frequency"]
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self.acpki = acpki
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self.rustc_cfg = dict()
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@ -167,7 +166,7 @@ class GenericMaster(SoCCore):
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ident = description["variant"]
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if self.acpki:
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ident = "acpki_" + ident
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SoCCore.__init__(self, platform=platform, csr_data_width=32, ident=ident)
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SoCCore.__init__(self, platform=platform, csr_data_width=32, ident=ident, ps_cd_sys=False)
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platform.add_platform_command("create_clock -name clk_fpga_0 -period 8 [get_pins \"PS7/FCLKCLK[0]\"]")
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platform.add_platform_command("set_input_jitter clk_fpga_0 0.24")
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@ -179,14 +178,20 @@ class GenericMaster(SoCCore):
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self.submodules.drtio_transceiver = gtx_7series.GTX(
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clock_pads=platform.request("clk_gtp"),
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pads=data_pads,
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sys_clk_freq=sys_clk_freq)
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clk_freq=clk_freq)
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self.csr_devices.append("drtio_transceiver")
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self.crg = self.ps7 # HACK for eem_7series to find the clock
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self.submodules.sys_crg = zynq_clocking.SYSCRG(self.platform, self.drtio_transceiver.gtps[0].txoutclk)
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txout_buf = Signal()
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txout_buf.attr.add("keep")
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self.specials += Instance("BUFG", i_I=self.drtio_transceiver.gtxs[0].txoutclk, o_O=txout_buf)
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self.submodules.sys_crg = zynq_clocking.SYSCRG(self.platform,
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self.ps7,
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txout_buf)
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self.csr_devices.append("sys_crg")
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self.crg = self.ps7 # HACK for eem_7series to find the clock
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# another hack since ps7 itself does not have cd_sys anymore
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self.crg.cd_sys = self.sys_crg.cd_sys
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fix_serdes_timing_path(platform)
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self.rustc_cfg["has_si5324"] = None
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self.rustc_cfg["si5324_soft_reset"] = None
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@ -281,8 +286,7 @@ class GenericMaster(SoCCore):
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class GenericSatellite(SoCCore):
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def __init__(self, description, acpki=False):
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sys_clk_freq = 125e6
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rtio_clk_freq = description["rtio_frequency"]
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clk_freq = description["rtio_frequency"]
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self.acpki = acpki
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self.rustc_cfg = dict()
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@ -294,23 +298,30 @@ class GenericSatellite(SoCCore):
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ident = description["variant"]
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if self.acpki:
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ident = "acpki_" + ident
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SoCCore.__init__(self, platform=platform, csr_data_width=32, ident=ident)
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SoCCore.__init__(self, platform=platform, csr_data_width=32, ident=ident, ps_cd_sys=False)
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platform.add_platform_command("create_clock -name clk_fpga_0 -period 8 [get_pins \"PS7/FCLKCLK[0]\"]")
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platform.add_platform_command("set_input_jitter clk_fpga_0 0.24")
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self.crg = self.ps7 # HACK for eem_7series to find the clock
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self.submodules.sys_crg = zynq_clocking.SYSCRG(self.platform, self.drtio_transceiver.gtps[0].txoutclk)
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self.csr_devices.append("sys_crg")
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data_pads = [platform.request("sfp", i) for i in range(4)]
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self.submodules.drtio_transceiver = gtx_7series.GTX(
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clock_pads=platform.request("clk_gtp"),
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pads=data_pads,
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sys_clk_freq=sys_clk_freq)
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clk_freq=clk_freq)
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self.csr_devices.append("drtio_transceiver")
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txout_buf = Signal()
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txout_buf.attr.add("keep")
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self.specials += Instance("BUFG", i_I=self.drtio_transceiver.gtxs[0].txoutclk, o_O=txout_buf)
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self.submodules.sys_crg = zynq_clocking.SYSCRG(self.platform,
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self.ps7,
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txout_buf)
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self.csr_devices.append("sys_crg")
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self.crg.cd_sys = self.sys_crg.cd_sys
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self.rtio_channels = []
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has_grabber = any(peripheral["type"] == "grabber" for peripheral in description["peripherals"])
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if has_grabber:
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@ -396,7 +407,7 @@ class GenericSatellite(SoCCore):
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self.submodules.cri_con = rtio.CRIInterconnectShared(
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[self.drtiosat.cri],
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[self.local_io.cri] + self.drtio_cri,
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mode="sync", enable_routing=True)
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enable_routing=True)
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self.csr_devices.append("cri_con")
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self.submodules.routing_table = rtio.RoutingTableAccess(self.cri_con)
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@ -405,31 +416,22 @@ class GenericSatellite(SoCCore):
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self.submodules.rtio_moninj = rtio.MonInj(self.rtio_channels)
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self.csr_devices.append("rtio_moninj")
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rtio_clk_period = 1e9/rtio_clk_freq
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self.rustc_cfg["rtio_frequency"] = str(rtio_clk_freq/1e6)
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rtio_clk_period = 1e9/clk_freq
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self.rustc_cfg["rtio_frequency"] = str(clk_freq/1e6)
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self.submodules.siphaser = SiPhaser7Series(
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si5324_clkin=platform.request("cdr_clk"),
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rx_synchronizer=self.rx_synchronizer,
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ultrascale=False,
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rtio_clk_freq=self.drtio_transceiver.rtio_clk_freq)
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platform.add_false_path_constraints(
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self.crg.cd_sys.clk, self.siphaser.mmcm_freerun_output)
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self.csr_devices.append("siphaser")
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self.rustc_cfg["has_si5324"] = None
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self.rustc_cfg["has_siphaser"] = None
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self.rustc_cfg["si5324_soft_reset"] = None
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gtx0 = self.drtio_transceiver.gtxs[0]
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platform.add_period_constraint(gtx0.txoutclk, rtio_clk_period)
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platform.add_period_constraint(gtx0.rxoutclk, rtio_clk_period)
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platform.add_false_path_constraints(
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self.crg.cd_sys.clk,
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gtx0.txoutclk, gtx0.rxoutclk)
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for gtx in self.drtio_transceiver.gtxs[1:]:
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platform.add_period_constraint(gtx.rxoutclk, rtio_clk_period)
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platform.add_false_path_constraints(
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self.crg.cd_sys.clk, gtx.rxoutclk)
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if has_grabber:
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self.rustc_cfg["has_grabber"] = None
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