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kasli_soc: support clock switch on drtio configs

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This commit is contained in:
mwojcik 2023-01-20 14:41:35 +08:00
parent dba8194f09
commit aa0760e4ab
1 changed files with 27 additions and 25 deletions
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50
src/gateware/kasli_soc.py
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@ -154,8 +154,7 @@ class GenericStandalone(SoCCore):
class GenericMaster(SoCCore): class GenericMaster(SoCCore):
def __init__(self, description, acpki=False): def __init__(self, description, acpki=False):
sys_clk_freq = 125e6 clk_freq = description["rtio_frequency"]
rtio_clk_freq = description["rtio_frequency"]
self.acpki = acpki self.acpki = acpki
self.rustc_cfg = dict() self.rustc_cfg = dict()
@ -167,7 +166,7 @@ class GenericMaster(SoCCore):
ident = description["variant"] ident = description["variant"]
if self.acpki: if self.acpki:
ident = "acpki_" + ident ident = "acpki_" + ident
SoCCore.__init__(self, platform=platform, csr_data_width=32, ident=ident) SoCCore.__init__(self, platform=platform, csr_data_width=32, ident=ident, ps_cd_sys=False)
platform.add_platform_command("create_clock -name clk_fpga_0 -period 8 [get_pins \"PS7/FCLKCLK[0]\"]") platform.add_platform_command("create_clock -name clk_fpga_0 -period 8 [get_pins \"PS7/FCLKCLK[0]\"]")
platform.add_platform_command("set_input_jitter clk_fpga_0 0.24") platform.add_platform_command("set_input_jitter clk_fpga_0 0.24")
@ -179,14 +178,20 @@ class GenericMaster(SoCCore):
self.submodules.drtio_transceiver = gtx_7series.GTX( self.submodules.drtio_transceiver = gtx_7series.GTX(
clock_pads=platform.request("clk_gtp"), clock_pads=platform.request("clk_gtp"),
pads=data_pads, pads=data_pads,
sys_clk_freq=sys_clk_freq) clk_freq=clk_freq)
self.csr_devices.append("drtio_transceiver") self.csr_devices.append("drtio_transceiver")
self.crg = self.ps7 # HACK for eem_7series to find the clock txout_buf = Signal()
self.submodules.sys_crg = zynq_clocking.SYSCRG(self.platform, self.drtio_transceiver.gtps[0].txoutclk) txout_buf.attr.add("keep")
self.specials += Instance("BUFG", i_I=self.drtio_transceiver.gtxs[0].txoutclk, o_O=txout_buf)
self.submodules.sys_crg = zynq_clocking.SYSCRG(self.platform,
self.ps7,
txout_buf)
self.csr_devices.append("sys_crg") self.csr_devices.append("sys_crg")
self.crg = self.ps7 # HACK for eem_7series to find the clock
# another hack since ps7 itself does not have cd_sys anymore # another hack since ps7 itself does not have cd_sys anymore
self.crg.cd_sys = self.sys_crg.cd_sys self.crg.cd_sys = self.sys_crg.cd_sys
fix_serdes_timing_path(platform)
self.rustc_cfg["has_si5324"] = None self.rustc_cfg["has_si5324"] = None
self.rustc_cfg["si5324_soft_reset"] = None self.rustc_cfg["si5324_soft_reset"] = None
@ -281,8 +286,7 @@ class GenericMaster(SoCCore):
class GenericSatellite(SoCCore): class GenericSatellite(SoCCore):
def __init__(self, description, acpki=False): def __init__(self, description, acpki=False):
sys_clk_freq = 125e6 clk_freq = description["rtio_frequency"]
rtio_clk_freq = description["rtio_frequency"]
self.acpki = acpki self.acpki = acpki
self.rustc_cfg = dict() self.rustc_cfg = dict()
@ -294,23 +298,30 @@ class GenericSatellite(SoCCore):
ident = description["variant"] ident = description["variant"]
if self.acpki: if self.acpki:
ident = "acpki_" + ident ident = "acpki_" + ident
SoCCore.__init__(self, platform=platform, csr_data_width=32, ident=ident) SoCCore.__init__(self, platform=platform, csr_data_width=32, ident=ident, ps_cd_sys=False)
platform.add_platform_command("create_clock -name clk_fpga_0 -period 8 [get_pins \"PS7/FCLKCLK[0]\"]") platform.add_platform_command("create_clock -name clk_fpga_0 -period 8 [get_pins \"PS7/FCLKCLK[0]\"]")
platform.add_platform_command("set_input_jitter clk_fpga_0 0.24") platform.add_platform_command("set_input_jitter clk_fpga_0 0.24")
self.crg = self.ps7 # HACK for eem_7series to find the clock self.crg = self.ps7 # HACK for eem_7series to find the clock
self.submodules.sys_crg = zynq_clocking.SYSCRG(self.platform, self.drtio_transceiver.gtps[0].txoutclk)
self.csr_devices.append("sys_crg")
data_pads = [platform.request("sfp", i) for i in range(4)] data_pads = [platform.request("sfp", i) for i in range(4)]
self.submodules.drtio_transceiver = gtx_7series.GTX( self.submodules.drtio_transceiver = gtx_7series.GTX(
clock_pads=platform.request("clk_gtp"), clock_pads=platform.request("clk_gtp"),
pads=data_pads, pads=data_pads,
sys_clk_freq=sys_clk_freq) clk_freq=clk_freq)
self.csr_devices.append("drtio_transceiver") self.csr_devices.append("drtio_transceiver")
txout_buf = Signal()
txout_buf.attr.add("keep")
self.specials += Instance("BUFG", i_I=self.drtio_transceiver.gtxs[0].txoutclk, o_O=txout_buf)
self.submodules.sys_crg = zynq_clocking.SYSCRG(self.platform,
self.ps7,
txout_buf)
self.csr_devices.append("sys_crg")
self.crg.cd_sys = self.sys_crg.cd_sys
self.rtio_channels = [] self.rtio_channels = []
has_grabber = any(peripheral["type"] == "grabber" for peripheral in description["peripherals"]) has_grabber = any(peripheral["type"] == "grabber" for peripheral in description["peripherals"])
if has_grabber: if has_grabber:
@ -396,7 +407,7 @@ class GenericSatellite(SoCCore):
self.submodules.cri_con = rtio.CRIInterconnectShared( self.submodules.cri_con = rtio.CRIInterconnectShared(
[self.drtiosat.cri], [self.drtiosat.cri],
[self.local_io.cri] + self.drtio_cri, [self.local_io.cri] + self.drtio_cri,
mode="sync", enable_routing=True) enable_routing=True)
self.csr_devices.append("cri_con") self.csr_devices.append("cri_con")
self.submodules.routing_table = rtio.RoutingTableAccess(self.cri_con) self.submodules.routing_table = rtio.RoutingTableAccess(self.cri_con)
@ -405,31 +416,22 @@ class GenericSatellite(SoCCore):
self.submodules.rtio_moninj = rtio.MonInj(self.rtio_channels) self.submodules.rtio_moninj = rtio.MonInj(self.rtio_channels)
self.csr_devices.append("rtio_moninj") self.csr_devices.append("rtio_moninj")
rtio_clk_period = 1e9/rtio_clk_freq rtio_clk_period = 1e9/clk_freq
self.rustc_cfg["rtio_frequency"] = str(rtio_clk_freq/1e6) self.rustc_cfg["rtio_frequency"] = str(clk_freq/1e6)
self.submodules.siphaser = SiPhaser7Series( self.submodules.siphaser = SiPhaser7Series(
si5324_clkin=platform.request("cdr_clk"), si5324_clkin=platform.request("cdr_clk"),
rx_synchronizer=self.rx_synchronizer, rx_synchronizer=self.rx_synchronizer,
ultrascale=False, ultrascale=False,
rtio_clk_freq=self.drtio_transceiver.rtio_clk_freq) rtio_clk_freq=self.drtio_transceiver.rtio_clk_freq)
platform.add_false_path_constraints(
self.crg.cd_sys.clk, self.siphaser.mmcm_freerun_output)
self.csr_devices.append("siphaser") self.csr_devices.append("siphaser")
self.rustc_cfg["has_si5324"] = None self.rustc_cfg["has_si5324"] = None
self.rustc_cfg["has_siphaser"] = None self.rustc_cfg["has_siphaser"] = None
self.rustc_cfg["si5324_soft_reset"] = None self.rustc_cfg["si5324_soft_reset"] = None
gtx0 = self.drtio_transceiver.gtxs[0] gtx0 = self.drtio_transceiver.gtxs[0]
platform.add_period_constraint(gtx0.txoutclk, rtio_clk_period)
platform.add_period_constraint(gtx0.rxoutclk, rtio_clk_period)
platform.add_false_path_constraints( platform.add_false_path_constraints(
self.crg.cd_sys.clk,
gtx0.txoutclk, gtx0.rxoutclk) gtx0.txoutclk, gtx0.rxoutclk)
for gtx in self.drtio_transceiver.gtxs[1:]:
platform.add_period_constraint(gtx.rxoutclk, rtio_clk_period)
platform.add_false_path_constraints(
self.crg.cd_sys.clk, gtx.rxoutclk)
if has_grabber: if has_grabber:
self.rustc_cfg["has_grabber"] = None self.rustc_cfg["has_grabber"] = None