libboard_artiq: added mem.rs, yet to fix drtioaux
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@ -1,35 +1,28 @@
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use core::slice;
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use crc;
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use io::{ProtoRead, ProtoWrite, Cursor, Error as IoError};
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//use board_misoc::{mem::DRTIOAUX_MEM}; // <- port
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//^ uses generated files (like csr, but mem) - todo check after initial generation
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use mem::mem::DRTIOAUX_MEM;
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use pl::csr::DRTIOAUX;
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use drtioaux_proto::Error as ProtocolError;
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use crate::drtioaux_proto::Error as ProtocolError;
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use libboard_zynq::{timer::GlobalTimer, time::Milliseconds};
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pub use drtioaux_proto::Packet;
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pub use crate::drtioaux_proto::Packet;
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// this is parametric over T because there's no impl Fail for !.
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#[derive(Fail, Debug)]
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#[derive(Debug)]
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pub enum Error<T> {
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#[fail(display = "gateware reported error")]
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GatewareError,
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#[fail(display = "packet CRC failed")]
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CorruptedPacket,
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#[fail(display = "link is down")]
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LinkDown,
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#[fail(display = "timed out waiting for data")]
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TimedOut,
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#[fail(display = "unexpected reply")]
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UnexpectedReply,
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#[fail(display = "routing error")]
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RoutingError,
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#[fail(display = "protocol error: {}", _0)]
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Protocol(#[cause] ProtocolError<T>)
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Protocol(ProtocolError<T>)
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}
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impl<T> From<ProtocolError<T>> for Error<T> {
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@ -2,10 +2,14 @@
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#![feature(never_type)]
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extern crate log;
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extern crate crc;
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extern crate failure;
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extern crate failure_derive;
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extern crate libboard_zynq;
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extern crate libconfig;
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extern crate libcortex_a9;
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extern crate log_buffer;
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extern crate io;
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// has csr; taken from runtime main
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#[path = "../../../build/pl.rs"]
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@ -13,6 +17,11 @@ pub mod pl;
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#[cfg(has_drtio)]
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pub mod drtioaux;
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// for now, memory map is only needed for DRTIO firmware
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#[cfg(has_drtio)]
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#[path = "../../../build/mem.rs"]
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pub mod mem;
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pub mod drtio_routing;
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pub mod logger;
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