From a82e7a332bd1091b46f618f5ab438e2354e1d324 Mon Sep 17 00:00:00 2001 From: mwojcik Date: Fri, 29 Oct 2021 09:56:44 +0800 Subject: [PATCH] gateware: kasli_soc: fix missing si5324 support --- src/gateware/kasli_soc.py | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/src/gateware/kasli_soc.py b/src/gateware/kasli_soc.py index fa45fe8..da376ea 100755 --- a/src/gateware/kasli_soc.py +++ b/src/gateware/kasli_soc.py @@ -113,8 +113,8 @@ class GenericStandalone(SoCCore): platform.add_platform_command("create_clock -name clk_fpga_0 -period 8 [get_pins \"PS7/FCLKCLK[0]\"]") platform.add_platform_command("set_input_jitter clk_fpga_0 0.24") - self.rustc_cfg["HAS_SI5324"] = None - self.rustc_cfg["SI5324_SOFT_RESET"] = None + self.rustc_cfg["has_si5324"] = None + self.rustc_cfg["si5324_soft_reset"] = None self.crg = self.ps7 # HACK for eem_7series to find the clock self.submodules.rtio_crg = RTIOCRG(self.platform) @@ -393,6 +393,9 @@ class GenericSatellite(SoCCore): self.add_memory_group("drtioaux_mem", drtioaux_memory_group) self.add_csr_group("drtiorep", drtiorep_csr_group) + self.rustc_cfg["has_si5324"] = None + self.rustc_cfg["si5324_soft_reset"] = None + if self.acpki: self.rustc_cfg["ki_impl"] = "acp" self.submodules.rtio = acpki.KernelInitiator(self.rtio_tsc,