diff --git a/src/gateware/zc706.py b/src/gateware/zc706.py
index 52dda90..a6cd746 100755
--- a/src/gateware/zc706.py
+++ b/src/gateware/zc706.py
@@ -149,6 +149,26 @@ leds_fmc33 = [
     ("user_led_33", 3, Pins("A17"), IOStandard("LVCMOS15")),
 ]
 
+# todo: verify if gpio pins/expansion port on xadc is the same as on kc705
+_ams101_dac = [
+    ("ams101_dac", 0,
+        Subsignal("ldac", Pins("XADC:GPIO0")),
+        Subsignal("clk", Pins("XADC:GPIO1")),
+        Subsignal("mosi", Pins("XADC:GPIO2")),
+        Subsignal("cs_n", Pins("XADC:GPIO3")),
+        IOStandard("LVTTL")
+     )
+]
+
+_sdcard_spi_33 = [
+    ("sdcard_spi_33", 0,
+        Subsignal("miso", Pins("D20"), Misc("PULLUP=TRUE")),
+        Subsignal("clk", Pins("B20")),
+        Subsignal("mosi", Pins("J18")),
+        Subsignal("cs_n", Pins("H18")),
+        IOStandard("LVCMOS33")
+    )
+]
 
 class NIST_CLOCK(ZC706):
     """
@@ -160,10 +180,11 @@ class NIST_CLOCK(ZC706):
         platform = self.platform
         platform.add_extension(nist_clock.fmc_adapter_io)
         platform.add_extension(leds_fmc33)
+        platform.add_extension(_ams101_dac)
+        platform.add_extension(_sdcard_spi_33)
 
         rtio_channels = []
 
-
         for i in range(16):
             if i % 4 == 3:
                 phy = ttl_serdes_7series.InOut_8X(platform.request("ttl", i))
@@ -179,7 +200,7 @@ class NIST_CLOCK(ZC706):
             self.submodules += phy
             rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=512))
 
-        # todo: figure out pins for that on zc706
+        # todo: figure out what to do since zc706 has no SMA I/O
         # phy = ttl_serdes_7series.InOut_8X(platform.request("user_sma_gpio_n_33"))
         # self.submodules += phy
         # rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=512))
@@ -189,19 +210,19 @@ class NIST_CLOCK(ZC706):
         self.submodules += phy
         rtio_channels.append(rtio.Channel.from_phy(phy))
 
-        # ams101_dac = self.platform.request("ams101_dac", 0)
-        # phy = ttl_simple.Output(ams101_dac.ldac)
-        # self.submodules += phy
-        # rtio_channels.append(rtio.Channel.from_phy(phy))
+        ams101_dac = self.platform.request("ams101_dac", 0)
+        phy = ttl_simple.Output(ams101_dac.ldac)
+        self.submodules += phy
+        rtio_channels.append(rtio.Channel.from_phy(phy))
 
         phy = ttl_simple.ClockGen(platform.request("la32_p"))
         self.submodules += phy
         rtio_channels.append(rtio.Channel.from_phy(phy))
 
-        # phy = spi2.SPIMaster(ams101_dac)
-        # self.submodules += phy
-        # rtio_channels.append(rtio.Channel.from_phy(
-        #     phy, ififo_depth=4))
+        phy = spi2.SPIMaster(ams101_dac)
+        self.submodules += phy
+        rtio_channels.append(rtio.Channel.from_phy(
+            phy, ififo_depth=4))
 
         for i in range(3):
             phy = spi2.SPIMaster(self.platform.request("spi", i))
@@ -209,11 +230,10 @@ class NIST_CLOCK(ZC706):
             rtio_channels.append(rtio.Channel.from_phy(
                 phy, ififo_depth=128))
 
-        # todo check sdcard spi pins on zc706 (if applicable)
-        # phy = spi2.SPIMaster(platform.request("sdcard_spi_33"))
-        # self.submodules += phy
-        # rtio_channels.append(rtio.Channel.from_phy(
-        #     phy, ififo_depth=4))
+        phy = spi2.SPIMaster(platform.request("sdcard_spi_33"))
+        self.submodules += phy
+        rtio_channels.append(rtio.Channel.from_phy(
+            phy, ififo_depth=4))
 
         phy = dds.AD9914(platform.request("dds"), 11, onehot=True)
         self.submodules += phy
@@ -236,6 +256,7 @@ class NIST_QC2(ZC706):
         platform = self.platform
         platform.add_extension(nist_qc2.fmc_adapter_io)
         platform.add_extension(leds_fmc33)
+        platform.add_extension(_ams101_dac)
 
         rtio_channels = []
 
@@ -253,10 +274,10 @@ class NIST_QC2(ZC706):
         self.submodules += phy
         rtio_channels.append(rtio.Channel.from_phy(phy))
 
-        # ams101_dac = self.platform.request("ams101_dac", 0)
-        # phy = ttl_simple.Output(ams101_dac.ldac)
-        # self.submodules += phy
-        # rtio_channels.append(rtio.Channel.from_phy(phy))
+        ams101_dac = self.platform.request("ams101_dac", 0)
+        phy = ttl_simple.Output(ams101_dac.ldac)
+        self.submodules += phy
+        rtio_channels.append(rtio.Channel.from_phy(phy))
 
         # CLK0, CLK1 are for clock generators, on backplane SMP connectors
         for i in range(2):
@@ -265,10 +286,10 @@ class NIST_QC2(ZC706):
             self.submodules += phy
             rtio_channels.append(rtio.Channel.from_phy(phy))
         
-        # phy = spi2.SPIMaster(ams101_dac)
-        # self.submodules += phy
-        # rtio_channels.append(rtio.Channel.from_phy(
-        #     phy, ififo_depth=4))
+        phy = spi2.SPIMaster(ams101_dac)
+        self.submodules += phy
+        rtio_channels.append(rtio.Channel.from_phy(
+            phy, ififo_depth=4))
 
         for i in range(4):
             phy = spi2.SPIMaster(self.platform.request("spi", i))